SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (102515)4/6/2000 1:02:00 AM
From: Charles R  Read Replies (1) of 1575844
 
<It has been my observation that system level performance is limited by two major factors- clock speed and memory latency.>

Agreed! I don't question that. I was talking about ipc.

<I'm not certain how the half cycle ALU will play out. It is entirely possible that will limit the clock speed of the chip. It will be interesting to see if that turns out to be a mistake. "No clever idea goes unpunished.">

We are on the same track here. Is it great minds think alike or something else ;-)

Other than process port this half cycle ALU may be the single largest risk to the Wilamette program. I am watching!
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News