Hi mishedlo; I don't see where the patent linked to has much to do with DDR DRAM. Here's the abstract:
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
patents.ibm.com
Regarding DDR, the control bus is essentially identical to SDRAM control. There is no device-select information on the control bus, as used by RDRAM, other than the traditional chip select and byte enables which are many decades old in the memory industry. Rambus, by contrast, allows the controller to address individual chips and set registers on them. DDR does not use double rates on the control bus information, unlike RDRAM. In addition, while DDR does use "substantially fewer bus lines than the number of bits in a single address", the technique it uses for this is precisely identical to the one in SDRAM, and that technique is identical to the one first implemented on memory chips 10,000 times smaller than the current ones designed many decades ago. In fact, the row/column addressing scheme has been remarkably well preserved over the years. The Rambus addressing scheme, by contrast, is packetized, and is very much new.
The protocol for DDR and RDRAM, is completely different. Addresses are brought into DDR chips in two phases, row and column. This reduces the number of address lines by a factor of about two, but is not new in DDR, or in SDRAM. Multiplexed address busses in DRAM has been standard since the 4Kx1 chips that came out 10 years before Rambus started. RDRAM, by contrast, takes address information from a much smaller number of lines, and at a much higher rate. DDR doesn't infringe on any of this.
That there would be similarities between input/output structures for late 20th century integrated circuits should not be a surprise, but those patents are from way back. There are no innovations in the I/O of DDR, except the concept of arranging for the chip being read to also send out a synchronizing clock. But DDR DRAM can be used without this feature, in fact the Xilinx DDR DRAM reference design doesn't receive the DQS clocks from the DDR, but only drives them. Look on page 7. Note that DQS is an output only, it is not brought back into the Xilinx FPGA:
xilinx.com
The technique of sending the clock along with the data is ancient in the electronics industry, it will be described in pretty much any high end book that describes techniques for getting ultra high performance from DRAM. I've definitely seen it in print 10 years ago, it may have been Horowitz and Hill, but I don't have my copy in front of me. In any case, that technique, as used in electronics, is prior art.
This can't be the patent that is being used by Rambus in their suit. It must be another one. Or possibly there is some other detail in the patent, not the primary thrust of the patent. But the technology described in the above abstract either differentiates RDRAM from from other memory types, or describes features that date back, in the commodity DRAM industry, to 20 years ago.
-- Carl
P.S. The Xilinx article linked above gives the skinny on RDRAM: "The main advantage of DDR SDRAMs over RDRAM is the use of the basic system infrastructure developed for PC-100. This eliminates the numerous design changes required by different "packet" protocols." In other words, RDRAM is different, though I would suggest that DDR has a lot of other advantages over RDRAM, including cost, ease of use, reliability, etc...
P.S. Here is the list of all Xilinx app notes. Try finding the one that explains how to use RDRAM. Good luck:
xilinx.com |
