Carl,
Good detective work. It probably is the Jeff Mitchell from Rambus (though he may or may not still be there).
So you should take whatever it says with a skeptical eye -- just as you should take Mr. Intel-hater Tom Pabst's site.
However, I found the following section in the IP portion of the site (http://www.dramreview.com/dramrev/ip/ip_rambus_patents.html). I believe, given the potential for insider information here, that it might spell out in more detail exactly what Rambus is claiming in their lawsuits. At least it might shed a little more light on the question we've wrestled with on the board about the lawsuit(s).
p.s. Carl, just because it's probably biased doesn't mean that quantitative sections of it are. If you can add to the list of products supporting DDR, I'm sure Jeff would include them (since he's already included some). Right now it shows a preponderence of products supporting RDRAM vs. DDR DRAM
Rambus Patents
Rambus has been awarded more than 70 patents. Do these patents truly embody fundamentally new DRAM technology? Or are they simply trivial improvements to existing technology? The answer will determine whether the broad claims in Rambus' patents, which appear to apply to all types of synchronous DRAMs, can be upheld as valid in court.
It may help to apply some historical context on the state of the industry when Rambus and other types of synchronous DRAMs were developed. The SDRAM was announced in 1992, at the same time as the RDRAM. Development of both had occurred simultaneously in the years proceeding the announcements. The DDR SDRAM was announced in 1996, well after RDRAM was in volume production. Several of Rambus' patents appear to read directly on both SDRAM and DDR SDRAM.
SDRAM
To help the JEDEC and the industry understand what SDRAM features and parameters were important to system manufacturers, Intel published the PC100 specification. This document describes the primary functionality of the mass market PC100 SDRAMs, and has been adopted by all DRAM manufacturers and incorporated into their devices. PC133 and DDR SDRAM are supersets of Intel's specification.
A feature of the SDRAM is a programmable mode register which, among other things, defines a delay between the time a read command is received and the time that the data is supplied by the device. This delay is termed the CAS latency.
This programmable CAS latency appears to be a direct implementation of the primary claim in Rambus patent No. 5953263. Claim 1 of the patent reads "A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises: a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request."
This claim, plain and simple, describes this programmable CAS latency function in an SDRAM type device. The links in the claim definition below show how each element of the claim is present in the PC100 specification. The three required elements in the claim, in addition to being a memory device, are:
* a programmable register (red in this figure)
* to store a value (yellow in this figure)
* which is representative of a delay time after which the memory device responds to a read request. (green arrow in this figure)
Each essential element of the claim is readily apparent from reading the specification or any manufacturer's SDRAM data sheet.
DDR SDRAM
At the January 10 SiliconTech symposium, Hyundai presented a slide summarizing the differences between an SDRAM and a DDR SDRAM. Of the four primary enhancements shown -- Differential Clocks, Internal DLL, 2-Bit Pre-fetch, and Bi-directional Data Strobes -- at least three of them appear as claims in Rambus patents.
Differential Clocks
Rambus patent No. 5915105, claim 36 reads: "A synchronous memory device having at least one memory section which includes a plurality of memory cells, wherein the memory device receives first and second external clock signals and outputs data on a bus, the memory device comprises: a plurality of output drivers, each output driver being coupled to the bus to output data on the bus synchronously with respect to the first and second external clock signals."
Examining each element of the claim individually and comparing it to the diagram shows a high correspondence between the claim and what is shown on the diagram.
A synchronous memory device having at least one memory section which includes a plurality of memory cells (This describes any generic memory device) wherein the memory device receives first and second external clock signals (The DDR block diagram shows two clocks, CLK and /CLK. These are the two complementary input clock signals which can equivalently be labeled the first and second clock signals) and outputs data on a bus, the memory device comprises: a plurality of output drivers, each output driver being coupled to the bus to output data on the bus synchronously with respect to the first and second external clock signals (The output drivers put data on the bus in a time sequence that is controlled by the input clock signals CLK and /CLK)
The first and second elements of the claim are obvious from the diagram, wheras the third is not shown in the diagram but is clearly described by the timing diagrams in a data sheet.
Internal DLL
Claim 40 of the same patent ('105) covers the internal DLL, reading: "The memory device of claim 36 further including clock receiver circuitry to receive the first and second external clock signals, and wherein the memory device further includes delay locked loop circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals."
The Hyundai diagram does not have the level of detail needed to show the clock receiver circuitry receiving the first and second external clock signals (CLK and /CLK from the example above), but the circuitry must exist in order for the device to operate. The delay locked loop is shown clearly. What also is not shown are first and second internal clock signals. It is possible for a DDR device to be implemented with only a single internal clock signal, although common engineering practice makes it more likely that the output of the DLL is a differential clock, which can be classified as first and second clock signals. In order to determine this conclusively, circuit diagrams would have to be obtained or created by disassembly of a device.
2-Bit Prefetch
Rambus patent No. 5995443 appears to read on the internal prefetch architecture also shown in Hyundai's diagram. This patent is much more specific than the examples above, and it would be difficult to determine from just a block diagram whether a device infringed.
More examples of Rambus IP reading on DDR SDRAM can be found in Volume 8, Issue 3 of Micron Technology's publication Design Line, "DDR SDRAM Functionality and Controller Read Data Capture."
On the front page of Rambus patent No. 5915105 is a diagram showing the input and ouput sections of an interface connected to an I/O pad. When this diagram is compared to Figures 1 and 2 from Micron's publication which describe the input and output sections of a DDR device, the similarities are remarkable.
The output portion of the DDR SDRAM diagrammed in Micron's Figure 1 is seemingly described by patent '105 claim 11, which reads: "A memory device comprising: a first circuit to generate at least one internal clock; and output circuitry having a pair of inputs and an output, the output being coupled to a bus, the output circuitry alternately selects one or the other of the pair of inputs in response to the at least one internal clock to provide even and odd bus cycle information to the bus."
The Micron diagram, as described in the claim, shows a pair of inputs to a mux with a single output, with the input source selected by the clock.
Micron's Figure 2 details the input section of a DDR SDRAM. Again, compared with the diagram on the Rambus patent, it is very similar. Claim 1 of the '105 patent appears to read on this directly: "A memory device comprising: a first circuit for receiving a bus clock from a bus and for generating at least one internal clock; and receiver circuitry coupled to the first circuit to receive the at least one internal clock, the receiver circuit samples information on the bus in response to the at least one internal clock to acquire even bus cycle information and odd bus cycle information from the bus."
The patent language appears to exactly describe the input logic shown in the Micron figure.
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