jim, <I could go on but I think you get the point.>
Yes, I got the point that you pretend to be too smart.
Let see:
<It does not discuss the following latency issues:
1)read/write turnaround latency>
The turnaround was specifically invented for bussed architectures and used by no less than Intel
itself, to specifically prevent collisions, and
even at 33MHz PCI bus, which is 24 times more relaxing
than Rambus.
The absence of turnaround in Rambus is the stupidest
thing in the whole approach, and probably adds a lot
to excessive power dissipation.
<2)Average latency for a cache fill from RDRAM>
???? You certainly mean a cacheline, do you?
But that's exactly where the definition of
latency comes from...
<3)The latency relationship between the L1, L2 caches and the RDRAM.>
If you would think harder, you will understand that
there is no relationship. The caches are behind
the FSB where the whole CPU-memory interaction occur.
You probably meant something like "advanced bufferng",
or "write combining", or maybe "victim caches"?
<4)The "dead time" effect of refresh cycles>
Since the underlying technology is the same - DRAM,
the final effect must be the same regardless
any particular external details.
<5) It fails to compare a memory system to RDRAM.>
The article deals with general concept of latency
and bandwidth in a computer system, so those little
details are irrelevant.
<6) The Front Side Bus bandwidth also plays a factor in the performance of the DRAM and RDRAM systems. It is not discussed.>
The FSB in question is the same - it is a PentiumPro
split-transaction bus. Therefore it contributes equally
in any memory architecture under discussion.
I could go on but I think you get the point. :) :)
- Ali "Screwdriver" and best buddy of Paul Engel.
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