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Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 94.82+2.7%Nov 26 3:59 PM EST

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To: Bilow who wrote (40460)4/20/2000 6:53:00 AM
From: Bilow  Read Replies (3) of 93625
 
Hi all; An addendum to the note on latency in i840 systems. A relevant link is:
developer.intel.com , pages 123 and 127.

Cache lines are 32 bytes only, but AGP PIPE# and SBA accesses can apparently go to 256 bytes. My guess is that the Intel bandwidth versus latency charts assume a lot of AGP activity, activity that increases the size of the typical transaction. Of course this is not my specialty, perhaps one of the Intel chipset experts will comment.

-- Carl

P.S. I should note that the "perfectly efficient" comments in the previous note require that the read and write accesses go to different banks, or to the same row if on the same bank. By perfectly efficient, I mean that there are no lost cycles due to the bus being turned around, or due to a collision on the control bus. By the way, VCRAM (sp?, it's getting late) takes a stab at reducing this efficiency caveat by saving multiple rows in each bank.
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