Hitachi borrowed the I/O and caching methods from its mainframe group and expects to introduce two- to 32-way systems shortly after Intel introduces Itanium later this year.
Who's going to be the loser when those Hitachi Itanium 32-way systems go on sale?
Sun?
IBM?
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Intel may license I/O scheme to link Itanium processors
By Anthony Cataldo
EE Times
(04/20/00, 6:11 p.m. EST)
eetimes.com
TAIPEI, Taiwan - Intel Corp. may license a proprietary I/O scheme that links its upcoming Itanium processors or clusters of processors. The I/O will allow OEMs to design systems with independent but connected multi-processor nodes rather than employing a common bus for all the 64-bit processors residing in the same box, according to a company official.
The I/O scheme can serve as a chip-to-chip or node-to-node link between single- or multiple-processor nodes in the same box. The I/O has a different purpose than the Intel-backed Infiniband I/O proposal, which is described as a switching fabric that will connect multiple boxes or peripherals like storage systems and eliminate the expensive crossbar switches found in mainframes.
Based on Intel's P6 bus, the proprietary I/O scheme is a wide, bidirectional link intended for short-distance connections of about 15 inches, said Mike Fister, vice president and general manager of Intel's Enterprise Server Group. Fister would not reveal the speed of the I/O.
The link will allow system designers, for example, to design an Itanium box connecting twin-processor nodes, each with its own memory subsystem. This will give designers more flexibility to expand the number of processors in a system, something that is difficult to do in systems with processors sharing a single I/O path.
"It's harder than hell to do eight CPUs on one bus," Fister said. "In an eight-way system, the I/O is tightly coupled, but you're going to want more I/O or computing density. You may want two-CPU nodes with big memory or another two-CPU node."
Intel may consider using the I/O to connect dual-core Itanium processors when transistor budgets make it economically feasible to combine two processors on a chip, Fister said.
First inquiries
Because the I/O would reside inside the box and is close to the processor, Intel is not interested in proposing it as an open standard but will consider licensing it to certain customers. Fister said some interested customers have already approached Intel.
Such a scheme will ostensibly help customers with little or no experience designing large, multiprocessor systems. Companies with mainframe experience, for example, are already designing multiprocessing systems with the Itanium processor, using internally developed I/O schemes.
Last January, Hitachi Ltd. announced plans for Itanium systems based on four-processor nodes, each with a memory subsystem, cache memory and a controller at each node to manage the data traffic among other nodes. Hitachi borrowed the I/O and caching methods from its mainframe group and expects to introduce two- to 32-way systems shortly after Intel introduces Itanium later this year.
The new I/O scheme is said to be related to a "scalability port," a cache-coherent link that allows OEMs to attach multiple four-way SMP processors into larger, more powerful systems with distributed system memory. That I/O scheme will be used in Intel's upcoming 870 chip set targeted at the next-generation 32-bit Foster processors due to ship late this year, and the 64-bit McKinley processors shipping next year. |
