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Politics : Formerly About Advanced Micro Devices

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To: Charles R who wrote (107322)	4/22/2000 3:04:00 AM
From: Joe NYC	Read Replies (2) of 1573004

Chuck, Now, an interesting question (for me at least): Who will debut a mass market part with memory interface embedded into the CPU? What time frame? What will that memory interface be? The Cyrix MediaGx suffered from the lack of L2, and tiny L1. Their more mainstream chip Mx (or Mxi?) with 6x86 core and 64K L1 never made it to the market because the whole chip did not scale. THe chip that was supposed to scale well M3 or Jalapeno (not what via is selling now as Cyrix 3) was a great concept, but never made it out of the design center. The next CPU with on-chip memory controller will be Timna, but the memory interface is Rambus. I think Timna is based on P6 core, but I don't know if it has any L2. The performance will be crippled by the Memory translation to SDRAM. The approach I would like AMD to take, if they ever go in this direction is to integrate only the memory controller, nothing else. For a mainstream market CPU that will never be used in multiprocessing environment, this would provide optimum performance. Joe

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