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Politics : Formerly About Advanced Micro Devices

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To: Scumbria who wrote (107320)4/22/2000 12:23:00 PM
From: milo_morai  Read Replies (1) of 1572943
 
AMD Athlon? Processor Architecture
The World's First Seventh-Generation x86 Processor: Delivering the Ultimate Performance for Cutting-Edge Software Applications

The AMD Athlon? processor is the first member of a new family of seventh-generation AMD processors designed to meet the computation-intensive requirements of cutting-edge software applications running on high-performance desktop systems, workstations, and servers.
The AMD Athlon processor is the world's most powerful x86 processor, outperforming Intel's Pentium© III processor and delivering the highest integer, floating point and 3D multimedia performance for applications running on x86 system platforms . The AMD Athlon provides industry-leading processing power for cutting-edge software applications, including digital content creation, digital photo editing, digital video, image compression, video encoding for streaming over the Internet, soft DVD, commercial 3D modeling, workstation-class computer-aided design (CAD), commercial desktop publishing, and speech recognition. It also offers the scalability and "peace-of-mind" reliability that IT managers and business users require for networked enterprise computing.

The AMD Athlon processor features the industry's first seventh-generation x86 microarchitecture, which is designed to support the growing processor and system bandwidth requirements of emerging software, graphics, I/O, and memory technologies. The AMD Athlon processor's high-speed execution core includes multiple x86 instruction decoders, a dual-ported 128KB split-L1 cache, three independent integer pipelines, three address calculation pipelines, and the x86 industry's first superscalar, fully pipelined, out-of-order, three-way floating point engine. The floating point engine is capable of delivering 4.0 Gflops of single-precision and more than 2.0 Gflops of double-precision floating point results at 1000 MHz for superior performance on numerically complex applications.

Download Entire PDF Document Here!

amd.com

amd.com

Taken from PDF file

WW W W HH H H II I I TT T T EE E E PP P P AA A A PP P P EE E E RR R R
Page 4 Architecture ? 52594A March 9, 2000
Pentium III and Pentium III Xeon processors. (See Table 1, Competitive Comparison, on
previous page.) The AMD Athlon processor features a superpipelined, nine-issue
superscalar microarchitecture optimized for high clock frequency. The AMD Athlon
processor has a large dual-ported 128KB split-L1 cache (64KB instruction cache + 64KB
data cache); a two-way, 2048-entry branch prediction table; multiple parallel x86
instruction decoders; and multiple integer and floating point schedulers for independent
superscalar, out-of-order, speculative execution of instructions. These elements are packed
into an aggressive processing pipeline that includes 10-stage integer and 15-stage floating
point pipelines.
The innovative AMD Athlon processor architecture implements the x86 instruction set
by internally decoding x86 instructions into fixed-length ?Macro-Ops? for higher
instruction throughput and increased processing power. The AMD Athlon processor
contains nine execution pipelines?three for address calculations, three for integer
calculations, and three for execution of MMX ? , 3DNow!, and x87 floating point
instructions.
Figure 1: AMD Athlon ? Processor Architecture Block Diagram
The AMD Athlon processor is binary-compatible with existing x86 software and
backwards compatible with applications optimized for MMX and 3DNow! instructions.
Using a data format and single-instruction multiple-data (SIMD) operations based on the
Load / Store Queue Unit
IEU AGU
Instruction Control Unit (72-entry)
Fetch/Decode
Control
2-way, 64KB Data Cache
32-entry L1 TLB/256-entry L2 TLB
3-Way x86 Instruction Decoders
FPU Register File(88-entry)
FADD
MMX
3DNow!
FStore
FMUL
MMX
3DNow!
IEU
Integer Scheduler (18-entry) FPU StackMap / Rename
L2 SRAMs System Interface
2-way, 64KB Instruction Cache
24-entry L1 TLB/256-entry L2 TLB
Predecode
Cache
Branch
Prediction Table
L2 Cache
Controller
Bus
Interface
Unit
FPU Scheduler (36-entry)
AGU IEU AGU
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