PMC-Sierra puts a Checkmate on the telecommunications industry with it's new CHESS Chip Set
PMC-Sierra Introduces New OC-48 Chip Set Architecture to Enable Next Generation Optical Network Deployment
The CHESS(TM) Channelized Chip Set Architecture Manages and Grooms Multi-service IP, Voice, Frame Relay and ATM Traffic Over Both SONET/SDH and DWDM Transport Equipment
VANCOUVER, B.C.--(BUSINESS WIRE)--April 24, 2000-- PMC-Sierra (Nasdaq: PMCS) today announced a new OC-48/OC-48c (2.5 Gbit/s) channelized architecture designed to completely revolutionize the way carrier and Internet Service Provider (ISP) networks are built, deployed and managed.
The CHESS (Channelizer Engine for SONET/SDH) chip set will allow for convergence of traditionally separate voice and data infrastructure into new, highly integrated carrier-class multi-service networks. The CHESS chip set is the industry's first and only chip set architecture allowing IP Routing, ATM/Frame Relay Switching, SONET/SDH digital cross connect/add-drop multiplexing and Dense Wavelength Division Multiplexing (DWDM) transport functionality to be built in a single, space-efficient hardware platform.
By replacing as many as five or six older, discrete network equipment elements, multi-service equipment networks utilizing the CHESS chip set will enable carriers and ISPs to provision a greater number of services more dynamically and at lower cost than ever before (see Figure 1). The CHESS chip set manages scarce SONET/SDH bandwidth and DWDM lambda wavelengths which are critical to the effective deployment and operation of true multi-service networks realizing "Any-Service, Any-User, Any-Channel". These networks can now utilize simplified software management layers making them significantly easier for carriers and ISPs to operate.
The CHESS Chip Set Upgrades MANs and Edge WANs
Which Are Critical to Carrier Business Growth
Carriers are urgently upgrading their infrastructure in emerging, high-growth Metropolitan Area Network (MAN) and edge Wide Area Network (WAN) regions to maintain and grow a very lucrative Service Level Agreement (SLA) provisioning business. These networks are ideally suited for SONET/SDH fiber backbones due to its scalability, availability and reliability. They are, however, highly under-utilized with the current OC-3/STM-1 (155 Mbit/s) and OC-12/STM-4 (622 Mbit/s) rate operation. The availability of the CHESS chip set provides an immediate upgrade path to OC-48/OC-48c/STM-16 (2.5 Gbit/s) rate operation. The CHESS chip set can also scale beyond 2.5 Gbit/s rate applications to support future OC-192/STM-64 applications running at 10Gbit/s rates.
The CHESS Chip Set Creates Next Generation, Carrier-Class,
Multi-Service and Optical Equipment
The edge of the network is a very challenging environment for a carrier or ISP to manage. MAN and edge WAN networks must not only aggregate the multi-protocol, low- and multi-rate DS0 (64 Kbit/s) to DS3 (45 Mbit/s) traffic from access customer premise regions, but are now also required to aggregate the wavelength lambda base rate of OC-48/OC-48c (2.5 Gbit/s) traffic from native DWDM transport networks. To meet these difficult requirements it is necessary to manage and groom SONET/SDH traffic at both STS-1/DS3 (51/45 Mbit/s) base access rate and at OC-48/STM-16 (2.5 Gbit/s) base DWDM rate granularities. The CHESS chip set is the first and only industry chip set to provide capability for such dual-rate SONET/SDH grooming capability.
The CHESS chip set provides SONET/SDH framing capability at each of the key OC-3, OC-12 and OC-48 optical line rates. Its STS-1 channelized traffic grooming capability allows for the development of dedicated service processing cards such as Packet-over-SONET, ATM and Frame Relay that replace entire, dedicated network service equipment utilized previously (see Figure 2 and Figure 3). But perhaps most importantly, the STS-1 grooming capability of the CHESS chip set will allow for sub-lambda wavelength processing such that multiple user services can be run over individual 2.5 Gbit/s lambda wavelengths (see Figure 4). This solves the optimal lambda utilization problem of provisioning more than a single user service per lambda and will help enable the creation of new multi-service optical equipment classes such as the integration of cross connects, add-drop multiplexers and switches.
"As the initial offering in our OC-48 strategy, the CHESS chip set architecture unveiling is a highly anticipated event for PMC-Sierra," said Steve Perna, PMC-Sierra's vice president and general manager, Optical Networking Division. "In conjunction with our key strategic customers, we have focused over the last 15 months on developing an OC-48 Internet Service Provider architecture that leverages significant system level expertise designed to optimize the scarce resources of network bandwidth, lambda wavelength and equipment form factor. The CHESS chip set architecture will significantly improve the ability of our customers to provide increased service level provisioning in their next-generation carrier-class equipment," he concluded.
Pricing, Packaging and Customer Support
The CHESS chip set architecture consists of five devices, each by itself unique in the industry for its high density and functionality, designed to operate seamlessly together (See Table 1).
-- SPECTRA-2488: OC-48/OC-48c/STM-16 and 4xOC-12/STM-4 SONET/SDH framer with STS-1/AU3 channelizer
-- SPECTRA-4x155: 4xOC-3/STM-1 SONET/SDH framer with STS-1/AU3 channelizer
-- TelecomBus Serializer (TBS): STS-48/STM-16 LVDS serializer and Auto Protection Switching (APS) tri-port
-- Transmission Switch Element (TSE): 768 channel STS-1/AU3 cross connect traffic groomer (40Gbit/s capacity)
-- S/UNI-MACH48: 48-channel Packet-Over-SONET Processor and ATM Cell processor with 48 channel STS-1 to DS3 asynchronous mapper
The SPECTRA-2488, TBS, TSE, and S/UNI-MACH48 are implemented in low power 0.18 micron CMOS technology, and the SPECTRA-4x155 in 0.35 micron CMOS. The PM5315/SPECTRA-2488 and PM5316/SPECTRA-4x155 are both packaged in 520 SBGA, the PM5310/TelecomBus Serializer (TBS) is packaged in 352 UBGA, and both the PM5372/Transmission Switch Element (TSE) and PM7390/S/UNI-MACH48 are packaged in 560 UBGA. Pricing in volume quantities is $99 for the PM5310/TBS, $324 for the PM5316/SPECTRA-4x155, $395 for the PM5315/SPECTRA-2488, $396 for the PM7390/S/UNI-MACH48 and $499 for the PM5372/TSE. PM5310/TBS and PM5372/TSE will be available as early as May 2000. Other samples will be available in the subsequent months. The CHESS chip set data sheets and technical overview are available on PMC-Sierra's web site at: pmc-sierra.com.
About PMC-Sierra
PMC-Sierra's extensive family of broadband communication semiconductors is enabling the equipment that makes up the backbone of the Internet. The company develops Internet Protocol (IP), ATM, SONET/SDH, T1/E1 and T3/E3 solutions for wide area network and Internet infrastructure equipment. PMC-Sierra's quality system is registered with the Quality Management Institute to the ISO 9001 standard. As co-founder of the SATURN(R) Development Group, PMC-Sierra works with over 30 other member companies to define and develop interoperable, standard-compliant solutions for high speed networking applications.
PMC-Sierra offers worldwide technical and sales support including a network of offices throughout North America, Europe and Asia. The company is publicly traded on the Nasdaq Stock Market under the symbol "PMCS". PMC-Sierra is included in the Nasdaq-100 Index (NDX) which contains the largest non-financial companies on the Nasdaq Stock Market. The Nasdaq-100 Index is the benchmark for the Nasdaq-100 Index Tracking Stock (AMEX: QQQ). For more information about PMC-Sierra, visit pmc-sierra.com.
Attachments Technical Glossary
Figure 1: CHESS Chip Set Consolidates Older Equipment into a Single, Multi-Service Platform
Figure 2: CHESS Chip Set Architecture
Figure 3: CHESS Chip Set Integrates Multiple Equipment Functions into Dedicated Card Designs
Figure 4: CHESS Chip Set Sub-Lambda Wavelength Processing Capability Grooms DWDM Traffic into IP, ATM and TDM Services
Table 1: CHESS Chip Set Architecture Device Details
Technical Glossary
ATM Asynchronous Transfer Mode
APS Automatic Protection Switching
AU Administrative Unit
CHESS Channelizer Engine for SONET/SDH
CMOS Complimentary Metal Oxide Semiconductor
DS Digital Signal
DSLAM Digital Subscriber Line Access Multiplexer
DWDM Dense Wavelength Division Multiplexing
FR Frame Relay
HDLC High-level Data Link Control
IP Internet Protocol
LVDS Low Voltage Differential Signalling
MAN Metropolitan Area Network
MUX Multiplexer
OC Optical Carrier
POS Packet-Over-SONET
SBGA Super Ball Grid Array
SDH Synchronous Digital Hierarchy - the European counterpart to SONET
SLA Service Level Agreement
SONET Synchronous Optical NETwork
STM Synchronous Transport Module
STS Sychronous Transport Signal
TBS TelecomBus Serializer
TDM Time Division Multiplexing
TSE Transmission Switch Element
UBGA Ultra Ball Grid Array
VT/TU SONET Virtual Tributaries/SDH Tributary Units
(c)Copyright PMC-Sierra, Inc. 2000. All rights reserved. SATURN(R)and S/UNI(R)are registered trademarks of PMC-Sierra, Inc. PMC-Sierra(TM), SPECTRA(TM)and CHESS(TM)are trademarks of PMC-Sierra, Inc.
--------------------------------------------------------------------------------
Contact:
PMC-Sierra
Susan Shaw, 604/415-6031
fax, 604/415-6011
sshaw@pmc-sierra.com
or
Benjamin Group (US Editorial)
Jeremiah Glodoveza, 408/559-6090
fax, 408/559-6188
jeremiah@benjamingroup.com
or
EML (European Editorial)
Jo Thompson, 011 44 20 8408 8000
fax, 011 44 20 8547 3950
jot@eml.com
siliconinvestor.com |
