EDA breakthroughs needed for future chip designs
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The power density problem is so bad that if current trends continue, future chips could reach 2,000 W/cm2, about as "hot" as a nuclear reactor, Borkar warned. This is due not only to an increase in active power, but also leakage power, which will make the situation worse.
One possible solution, he said, is to place more memory on-chip. Memory is more power-efficient than logic. Thus, Borkar said, "large integrated caches make more sense than larger units of logic."
But in general, Borkar said, designers will have to trade off some performance to reduce power. This might mean using static logic instead of the higher performance, but more power-hungry, domino logic. It means developing techniques for leakage control, like employing "sleep transistors," which Borkar said can provide a thousand-fold savings in leakage power. But this technique is very hard to implement, he said, and it cries out for automated CAD tools.
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