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Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 89.57+2.1%11:41 AM EST

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To: jhg_in_kc who wrote (40985)4/26/2000 11:15:00 PM
From: Ali Chen  Read Replies (1) of 93625
 
jhg..: <Slater failed to discuss in depth the benefits Rambus will provide..>
You probably mean low latency again?
In this case could you help me with the
following after-math:


discussions.hardwarecentral.com
==== begin quote ========
"I apologize upfront for being rude, but
it is impossible to hold this kind of
SDRAM abuse any more. Your arithmetics
need some serious correction.

You assume for PC100:
40 + (2 x 10) + (3 x 10) = 90ns for PC100 SDRAM

How the heck did you arrive to this?
Most contemporary SDRAM memory have
the following timing:

Precharge = 2 clocks,
Ras-to-Cas = 2 clocks,
Cas-to-Data = 2 clocks.

Therefore the correct arithmetics is:

(2+2+2)x10 = 60ns for a good PC100 SDRAM

For PC133 the same is true. But you
assume nonsense:
45 + (2 x 7.5) + (3 x 7.5) = 82.5ns for PC133 SDRAM

A good PC133 (say, Micron grade -7E)
can run 2-2-2 at full 133MHz,
therefore the correct answer again is:

(2+2+2)*7.5 = 45ns.

Only 45 nanoseconds!!! All the above
assumes the worst definition for
latency - from the end of previous
transaction to first Q-word of data.

Now please do your homework about
Rambus, but do not forget the following:

a) Cas-to-data delays on all chips
are artifically increased to be equal
to the longest path, or up to 7.5ns,
to avoid data collisions.
For your information, a 16-chip RIMM
is specified to have exactly 2.06ns
of finger-to-finger propagation time.
So two RIMMs are already 4.1ns, plus
controller-to-RIMM, plus between RIMMs.
So, the COL-to-data delay is 20ns+5ns at least.

b) The data from RAMBUS are coming in
16/18-bit words, while all chipset
internals operate at 64/72bits.
Therefore to assemble the whole
internal 64-bit word you need to wait
for the END of the 4-bit times, or
extra 10ns.

c) The Ras-to-Cas delay is always
8 clocks, or 20ns;

d) I have no idea how long it takes
to open a new page, but assuming that
the physics of DRAM is still the same,
it will take no less than 15-20ns as
for best PC133, but the whole RAMBUS
timing goes in chunks of 10ns,
therefore take 20ns as well.

Now do your math.***
<snip>

***(correct answer is 25+10+20+20 = 75 ns)
====== quote ends ===============

So, what's wrong with this "arithmetics"?
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