I saw that.. I was looking at this info..T-Birds L2 Cache- 16-way...
happy-cat.ne.jp
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00/04/28, 1:50pm - Whoa! Lookie-here ... the folks at Happy Cat have revealed some mildly shocking info about the Thunderbird. What's so bigwig here? The L2 cache is 16-way set associative, a level of associativity that frankly I believe has never been seen in x86 memory caches (please, correct me if I'm wrong). On top of this, if the L1 and L2 caches are exclusive to each other (as is the case on the Spitfire/Duron), the set associativity would increase to 18-way (16 for L2 plus 2 for L1). Um, at least, that's what I think the case is. I only recently pieced together what associativity is, so I'm tentative with anything that I say about it. ;)
The net effect here would be to decrease the cache miss rate. This is basically the same result that you'd get from increasing the size of the cache. Because of the increase in associativity, this 256KB L2 cache may very well be equivalent to or better than a 2-way (or 4-way, maybe?) 512KB on-die nonexclusive L2 cache (eg, in miss rate and such). I'd quote Hennessy/Patterson (sp?), but I don't think that Quantitative listed cache sizes above 128KB in that funky little miss rate table.
Now, I'm a much bigger fan of increasing cache size as opposed to increasing associativiy as a means of decreasing miss rates. I find it monumentally silly when people tout the "amazing" benefits of going from 2-way to 4-way. But I might be able to cheer on a move from 2-way to 18-way. We'll see, I guess.
jc-news.com
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