SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Joe NYC who wrote (108700)4/30/2000 11:04:00 PM
From: Dan3  Read Replies (2) of 1571911
 
Re: on a quad pumped bus, the transfer of information occurs on rising, falling edge, as well as high and low levels...

Hi Joe,

I don't think it can work that way. I'm no EE, but I'll try to explain why I think this is the case - maybe someone who really knows this stuff can tell me if I'm making any sense. To make it easier to visualize I think about a data string of 0 1 0 1. I'm pretty sure it would be running the data lines at twice the MHZ supported by the spec if it tried to communicate 4 bits in a cycle.

In other words, a wave (or cycle) has a peak and a trough. You can have it peak or not peak for one bit per cycle, trough or not trough for a second bit, but you can't get any more bits out of a wave than that. I suppose you could run the data lines at twice the frequency of the clock lines, but if you're designing to support those frequencies anyway, why not let the clock lines support the higher rates as well?

Does that make sense?

Regards,

Dan
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext