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Politics : Formerly About Advanced Micro Devices
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To: Dan3 who wrote (108710)4/30/2000 11:27:00 PM
From: Bilow  Read Replies (1) of 1572190
 
Hi Dan3; Re "Quad" pumped bus &c...

I don't know what Intel means with this, but in the SRAM
area, "QDR" or "Quad Data Rate" actually means separated
DIN and DOUT buses, with DDR on each bus. This means that
the design does offer 4x the rate of the usual bus width,
but they use twice the pins. This would be in keeping with
your assumption.

On the other hand, with the use of PLLs or DLLs, a true
quad data rate is possible, and really isn't a terribly
bad idea. I would rather limit myself to DDR, as the
frequencies you generate with that are no worse than the
ones you generate with QDR, but it has been very popular
recently to design with a slow system clock that every
board or chip converts to a higher frequency. This
reduces the frequency of your system clock. A lot of
PLL chips allow this.

If the PLL chips were set for 2x clock multiplication,
then you would have a DDR system. But if they happened
to be set for 4x, then you would have a QDR system.

-- Carl

P.S. I now see that I am supposed to include some wave forms...

Quad data rate system:

SysClk /-------\_______/-------\_______/-------\_______/
PllClk /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_
DataBus[] 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | B

Only SysClk and DataBus[] need exist outside the chip.
PllClk could be a signal internal to the ICs only.
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