Re Graphics memory and DDR: A test of "Carl's graphics memory rule of thumb"...
Nvidia released a bit of information about their next generation graphics controller:
Nvidia claims GeForce 2 provides visual realism
While the earlier GeForce's internal clock operated at 120 MHz and connected via a 300-MHz interface to double-data-rate SDRAM, its successor's clock runs at 200 MHz and contains a 333-MHz interface to 96 Mbytes of DDR SDRAM.
techweb.com
Given 96MBytes of memory, I would expect a bandwidth of around 96*120 = 11GB/sec. But the above article doesn't give the bus width. On the other hand, they do give a memory size of 96MB, so the bus is likely to have a width divisible by 3. Possible candidates are 96-bits, and 192 bits. The two candidates give bandwidths, at 333MHz, of 4GB/sec and 8GB/sec. The next highest size would be a 384-bit bus with BW of 16GB/sec, but that is clearly not possible (too many chips). So I expect that the board will have a BW of 8GB/sec on a 192-bit bus. This is 64-bits wider than the current 128-bit wide bus. Supposing that they are using x32 memory chips, this would require six chips, each with 16MB = 128Mb storage each.
So I predict, on the basis of the above information (i.e. assuming the EE-Times article is true), that they are using six 128Mb x32 DDR SDRAM chips. But this assumes that they are getting 333Mbits/sec out of their DDR data pins.
There is another possibility, and that is that when they talk about "333MHz" DDR chips, they are talking about the clock rate, and so have data transfer rates of 666MHz. (This is fast, but it is technically much easier than the 800MHz data rate that Rambus uses. The reason that it is easier is similar to the reason why AMD went with the LDT instead of a Rambus style interchip communication scheme. It is a lot easier to get a high speed system between just two chips on the same board, than it is to design one between 33 chips on four boards, ala RIMMs.) In that case, then it is my prediction that they have a 96-bit wide bus, with three x32 256Mb memory chips, or perhaps six x16 128Mb chips.
In either case, my prediction is for a BW of 8GB/sec.
-- Carl |
