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Politics : Formerly About Advanced Micro Devices

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To: Petz who wrote (109477)	5/5/2000 2:21:00 PM
From: Ali Chen	Read Replies (1) of 1576856

Petz, <the FSB (effectively 200 MHz) does not have to be changed to improve memory latency.> This contradicts with observations, and therefore is a fallacy. The EV6 bus overhead does exist. The "200MHz" is a good marketing ploy, but in fact all bus transactions are still granular on 100MHz clock and even worse. Thus the bus latency is directly added to the memory latency. In addition, there is so-called inter-domain "friction" if two different clock domains are involved. From the above it follows that the DDR will not help either. Sorry to disappoint you and some internal AMD platform evangelists. It is really disturbing to see how the (almost) brilliant processor design is dying in hands of ignorants. Regards, - Ali

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