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Politics : Formerly About Advanced Micro Devices
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To: Ali Chen who wrote (109483)5/6/2000 7:32:00 AM
From: pgerassi  Read Replies (1) of 1576648
 
Dear Ali:

When used with PC1600 (100Mhz(200Mhz DDR)) DDRSDRAM, synchronization domains do not exist between FSB and Memory bus. Assuming CAS2 PC1600, 5+1+1+1+1+1+1+1 (64 Byte Athlon xfer) becomes 4.5+.5+.5+.5+.5+.5+.5+.5. Thus, 12 cycle latency becomes 8 cycle latency. No FSB change is involved. Even CAS-3 PC1600 7(worst case)+7*.5 is 10.5 or 11 cycle. Using PC2100 (133-266 DDR) would get, worst to best case, 3+3+8*3/8=9 cycles to 2+2+8*3/8=7 cycles at 100 Mhz (200 DDR) FSB even if you add one for multi-domain latency.

It should be clear that DDRSDRAM will improve latency by transferring a cache line faster. Any improvements to initial latency are all the better.

Pete
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