See the routing on an i820 RDRAM mother board, with notes provided by Bilow.
These notes are for the i820 Chipset Design Guide Book. A perusal of this document leads to some fascinating insights into how RDRAM is actually used, and I think the technically inclined will find it fascinating reading:
developer.intel.com
The i820 is a chipset, but the main chip is the 82820 Memory Controller Hub. That is the chip that glues the processor to RDRAM. This is not the chip that screwed up on SDRAM recently, I haven't yet taken a look through the design guide for SDRAM versions of this chipset...
First of all, the pins required on the 82820 for the RDRAM interface are clearly delineated on page 30 (labeled 2-2). On that page, Figure 2-1 shows that the Direct RDRAM interface requires 81 pins. This is considerably larger than the usual quote of 33 pins, but the RSL pins are high current and so require a fairly larger number of power and ground pins. It should be noted that Hitachi is putting a x64 SDRAM into a 108-pin package, so the difference in pins between the two types of memory is no where near as large as the bandwidths per pin would suggest. Note that the AGP interface requires 77 pins, which is less than the Direct RDRAM interface. The maximum bandwidth on the AGP bus is 1066MB/s, which is a considerable fraction of the bandwidth that the memory interface provides. But it is true that the AGP interface doesn't have (or need) the control bandwidth that a memory system requires. Out of the 26 RSL Rambus signals, 18 of them are data, while the other 8 are control. Thus something like 70% of the RSL interface is devoted to data bandwidth, not control bandwidth. In addition, some of Rambus' CMOS signals have to be carefully routed, and are almost as much of a pain as the RSL signals.
The top layer motherboard figure is on page 33 (2-5). This is a routing example for a motherboard that uses RDRAM in an ATX form factor. You can see the RIMM modules as the two yellow tinged vertical columns on the right. The 82820 chip is to the left of them, is square, and is much shorter.
Go ahead and zoom in on the vicinity of the 82820. Visually, even people with no technical background will be able to recognize the parts of the board devoted to RDRAM routing as compared to the other parts. The part where the lines are all squiggly and are widely separated is the RDRAM routing area. The reason for all the squiggles is to make the path lengths the same. Since all the paths have to be the same length, the ones that would otherwise be too short are squiggled to make them longer. In addition, the RDRAM traces are widely separated. That is to prevent them from interfering with each other. The overall effect is that it looks sort of like cooked spaghetti.
The region directly below the 82820 chip has traces that are all running parallel and close together. This a region of routing between the 82820 and the AGP bus. The number of traces is something like 75. The lines are longer because the AGP bus is farther from the 82820 than the RIMM modules, but notice how the total width required is roughly the same as the width required by the 26 RSL lines of the RDRAM interface. This is a demonstration of how it is that even though Rambus reduces the number of traces required in an interface, it doesn't actually reduce the board surface area required.
Figure 2-6 is on the next page. The main routing feature of this page is the very wide connection from the 82820 chip to the CPU module. The wires leave the top left sides of the 82820 chip. You can again see the AGP connector, and the RIMM modules as well. Notice that the long straight AGP lines are missing from this plane, though there are AGP wires present on this plane. They are at the same position on the 82820 chip as the section of it that you saw in the above area, but the wires, instead of going all the way to the AGP, instead end in "vias". These vias connect to the straight lines in figure 2-5 on the previous page. These short little wires are called "escape" routes, because they allow the wires to escape from underneath the crowded 82820 (which is in a BGA package). Escape routing is what typically sets the required minimum number of layers in a PCB with high pin count BGA packages. Note that you can see more cooked spaghetti connecting the right side of the 82820 to the RIMM modules. These are RSL signals that didn't fit on the 2-5 layer. Note that other than the escape routing, both the CPU and the AGP connections fit onto single signal layers. Also note that the CPU connection includes extra wire to adjust wire lengths, but that they can be placed so close to each other that they are almost not noticeable.
The layers that provide power to the chips isn't shown, as they are typically pretty boring. They're described starting on page 42 (2-14) if you are interested.
Another consequence of adding the RDRAM interface is that the "stackup" has to be made differently. Inner layers have to be thinner, and this means that the motherboards are a wee bit more expensive than otherwise, though I would guess that the effect is nominal.
Page 37 (2-9)
Achieving a 28 ohm impedance with a traditional 7 mil prepreg requires 28 mil wide traces. These traces are too wide to break out [i.e. escape] of the two rows of RSL balls on the MCH. To reduce trace width, a 4.5 mil prepreg is required. This thinner prepreg allows 18 mil wide traces to meet the 28 ohm (+/- 10%) nominal impedance requirement. Also see page 150 (5-4)
Page 38 (2-10) gives further explanation for why Rambus' RSL signals are widely separated: "To maintain a nominal 28 ohm trace impedance, the RSL signals must be 18 mils wide. To control crosstalk and odd/even mode velocity deltas, there must be a 10 mil ground isolation trace routed between adjacent RSL signals. The 10 mil ground isolation traces must be connected to ground with a via every 1 inch. A 6 mil gap is required between the RSL signals and the ground isolation trace." In other words, the number of effective RSL signal lines is more than the 26 usually counted, but is about twice that. With extra vias required to ground the ground lines. The next two pages gives close-ups of the RSL routing for the two layers.
I hope that this i820 motherboard tour has been useful for those who have never seen the gerbers for such a board, and I will reference this post for people who make simple pin counts and conclude that money will be saved by reducing the size of motherboards. Engineering is a nasty world of compromises, and nothing comes free. The fluff that marketing puts out is always a gross simplification of what are very complex issues.
-- Carl
P.S. An interesting (but unimportant) peak power consumption screwup is on page 157 (6-5). |
