Pete, I think poor Anand was outgunned by the Rambus truth squad there. He started out pretty confused:
The Athlon, currently running off of the 1.06GB/s of memory bandwidth provided by PC133 SDRAM, will migrate to a 133MHz DDR FSB (effectively running at 266MHz) toward the end of this year. This translates into about 2.1GB/s of bandwidth present between the CPU and the North Bridge of the chipset (this path is otherwise referred to as the FSB). Combine that with the 1.06GB/s required by AGP 4X and 64-bit PCI running at 66MHz(528MB/s), and you get about 3.7GB/s of bandwidth that the memory interface must be capable of supplying or your AMD based system won't beable to operate at its peak. We just mentioned that the Athlon's PC133 SDRAM can currently only deliver 1.06GB/s of memory bandwidth, and even using DDR SDRAM, you're only going to increase that to 2.1GB/s, still only 57% of the total memory bandwidth we need for our nextgeneration AMD based systems.
Er, um, either I'm confused here or Anand is. 133 DDR FSB? I assume he's conflating the memory bus with the FSB here. Aside from that confusion, he seems to be swallowing whole some Intel line about the memory system needing to saturate all the other buses simultaneously. Which makes me note in passing the cleverness of Intel slipping into the equation this implicit assumption of everybody running AGP under a UMA interface, about the only way anybody'd ever come close to saturating AGP. Then there's this:
The trend in the computer industry has been towards lowering pin counts.
Er, um, a rather broad statement there, supported by exactly two examples, Rambus and some serial ATA proposal that hasn't exactly gone anywhere yet, to my knowledge. I sort of like firewrire, though.
Anyway, for raw bandwidth, I still like the nvidia x-box solution, which claimed 6.2 gbyte/second from a wide DDR interface. Who knows, though, Rambus may actually have its place, I didn't get really annoyed with the whole Rambus thing till I discovered the official Rambus policy of siccing the shareholders on anybody discussing the technology, along with the bogus no-criticism contracts with the memory makers and the bogus patent lawsuits.
Cheers, Dan. |
