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Politics : Formerly About Advanced Micro Devices
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To: Bert Herman who wrote (111664)5/20/2000 8:03:00 AM
From: Gopher Broke  Read Replies (2) of 1572896
 
I was just browsing the AMD presentation at the DDR conference and in the chipset section they place a lot of emphasis on the matching of bus speeds either side of the northbridge giving "significant benefits". One diagram has a special arrow marked "synchronous" tying together the host bus and the memory bus, implying to me that the northbridge can just pass through the memory requests?

It seems like a lot of discussion about memory latency considers DDR and RD in isolation rather than in the context of the bridge. Any hardware experts out there who can comment on the effect this bus synchronization through the northbridge might have on memory latency?
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