SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 95.26+3.1%Nov 14 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Tenchusatsu who wrote (43096)5/27/2000 3:35:00 PM
From: Joe NYC  Read Replies (1) of 93625
 
Tenchusatsu,

The key word in the name "ServerWorks" is "server." Platforms designed for higher-end servers are more expensive and more robust than platforms designed for desktops and workstations.

I think you will be hard pressed to find a single user application that needs all of the bandwidth of DDR-SDRAM. For example, Piii can't accept more that 800 MB/s to 1 GB/s, while DDR SDRAM can provide twice that amount. So any kind of realistic need for more than a single channel will be exclusively in servers.

For example, servers often require 12-layer motherboards.

I don't know the cost to design these, but as far as the cost to produce these motherboards, you could recoup the extra cost on the first 128 MB of SDRAM compared to RDRAM. Since the servers often need 1 GB or more memory, the cost of the motherboard is going to be penuts compared to the cost of the memory (in case it is RDRAM).

Besides, did you know that Intel's 450NX chipset, the first one to support 4-way Xeon and is still shipping today, uses quad-channel EDO? Bet you didn't. ;-)

Surprisingly, I did know. I was reading about a system that had as many as 16 DIMM (or SIMM?) slots for memory. One thing I noticed at that time was that the EDO memory for this system was extremely expensive (a multiple of the normal cost of memory) I don't know if the motherboard needs a non-standard memory.

On the other hand, I hear that API is designing a dual-processor Athlon chipset with dual-DDR channels, and it will use a single north bridge to do all that. Of course, that north bridge will require over 1,000 pins (not a trivial thing). And how many layers will that motherboard require? Probably more than six. (BTW, Intel's 840 chipset w/ dual RDRAM channels is a 6-layer motherboard.)

I don't think 840 will be in the same league as the API chip. I don't know how much we can rely on the benchmark in the article I posted, but the benchmarks clearly show that a single channel DDR outperforms a dual channel RDRAM (840).

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext