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This is the text of AMD's presentation at the DDR summit (no link):
Ron Huff: Thank you, Todd. This is quite an honor, to be invited to the DDR forum on behalf of AMD, I'm very happy to be a part of open industry standards for the purpose of
creating a new future standard for high performance memory. Today I plan to answer the question from a platform point of view, why is DDR so important? Why is it needed? To
try to put that into perspective, first what I'm going to do is explain our AMD strategy, platform strategy, and then get into showing how this all fits together and how DDR fits
into the performance equations for next generation Athlon platforms.
Starting off with, AMD's strategy is to offer platforms that span top to bottom of the PC market. We plan on moving beyond the success we've had in the consumer desktop and
mobile arena into the enterprise desktop workstation and server market. In order to do that, we need to continue moving forward on processors and optimized processors for
different markets. We are going to be introducing this year new versions of the Athlon core with an enhanced core that incorporates full speed on-chip L2 cache. In addition, we will be introducing our copper interconnect technology, which is well known to have very significant benefits for increasing the speed of microprocessors. As most of you know, AMD was the first to introduce a 1 gigahertz processor into the market and we believe this has been very good at stimulating demand for the industry as a whole. Next year we plan on introducing an eighth generation core, currently called SledgeHammer.This will be x.86-64. This product will not only have the capability to execute 64 bit instructions, but will also be optimized to compete in the high end of the x.86-32 bit market as well. In order to see this high performance processor, we will be introducing an interconnect technology we call LDT, which is a very high speed I/O bus which will be useful in creating a pipe in into the core logic of the system to enable next generation I/O technologies like 1394-B gigabit ethernet as well as PCIX.
Probably the most important aspect of our strategy is our core value. They are to work with the industry in open standards where we all work together. I think this forum today is an example of exactly the kind of cooperation and industry we would like to continue to see and support. I'd like to go over very quickly here some of the elements of our CPU roadmap this year.
We talked about the enhanced Athlon core that we will introduce in this year. We will have several versions, a version that is targeted for the performance desktop space, as well as a version that is targeted for the value space. We have recently introduced the brand of that processor called the AMD Duron. Previously it leaked out our code name, which was Spitfire, and this product will be introduced along with our Athlon version as well coming up here this year. We will also introduce a version of this core that will be optimized for workstations and servers. This will have a very large on chip L2 cache.
In addition we will have a mobile version which we are calling Corvette, which will be optimized for state-of-the-art performance and battery life performance in a mobile
environment.
Here again we talk about SledgeHammer, our next generation, eighth generation core. Let's see how DDR fits into our platform strategy for 2000. When we introduce, in the
second half of the year, DDR support, we will have chipsets from AMD, Via and ALi. The 760 chipset, which we are previewing today outside the door of this room, is a DDR
technology demonstration of this product which we intend to launch in the second half of this year. Most significantly it supports the DDR standard PC2100 and 1600. In the midrange space we will also be, as we work with our third party chipset vendors, introducing DMA, or sometimes known as SMA chipsets supporting PC133 and PC100.
And just give a few more points on feature set of the AMD 760 chipset, we'll also have a version called the 760MP, supporting 1 and 2 processors. It will support up to four
DIMMs, unbuffered and buffered DIMMS, a next generation ATA interface for disk drives. These are the enhancing features of these chipsets.
Now I'd like to kind of from an architecture point of view go over some of the capabilities of our DDR platform. First, as we mentioned, we will have an enhanced processor core running at much higher clock rates. This will increase the demand for memory bandwidth performance. In addition, we will be taking the already industry leading Athlon system bus, which runs at 200 megahertz, up to 266 megahertz, increasing the bandwidth by 33 percent. We'll introduce support for DDR memory, and what's very interesting is you can see here that both the host bus and the DDR memory are both operating at the same speeds. They're both operating at 266, or in case of lower
performance systems, 200 megahertz, but the significant thing is they're running synchronously.
From a system design point of view this is the path in the architecture of the platform that you want to optimize. You want to make sure that your processor to memory path is the
most optimized, most straight through. This is actually very unusual to see. If you look in the path there is always typically a mismatch. Now we have actually addressed this by creating a matched pair. We have two DDR buses running at 266 megahertz, both 64 bits wide.
This allows the north bridge to have a very straightforward low latency path to create high system performance. We also are introducing a version which will have a second memory hungry processor. To some extent we will be balancing it off by increasing the L2 caches. Many applications will still demand more bandwidth out of the main memory. This is where DDR comes into play. We talked about LDT. LDT will be
used as an interconnect technologist, a fatter pipe for the south bridge to enable the coming demand for high speed I/O. And here, just to kind of hit the high points of why
DDR is needed, what our customers tell us, AMD, for the most part we consider ourselves to be memory agnostic. We like DDR because of what customers tell us about it. We support DDR for that reason. We feel that, and we hear this from our customers, that it is the most cost-effective solution for advanced memory bandwidth on PC pricing curves. That's important. You need to make sure that your memory technology has a fundamental cost basis that allows it to continue to provide more value for similar or less
cost. And based on what we have been told by the memory vendors, we believe that we will have this advantage at launch where the cost premiums, at least from the manufacturing side, will be a single digit.
Of course market pricing will vary, but that's a very key point, because as production ramps up we think it will fall to manufacturing costs pricing. Also as we talked about,
DDR and Athlon frontside bus have a very natural affinity, as we spoke about before.This is one advantage, we are going to take this great advantage and exploit in our 760
chipset. From the benchmarking and performance side we have systems up and running, we're benchmarking now. What we can tell you is that DDR substantially increases performance, not just for benchmarks, but actually average applications that you have today will see a benefit of this performance. That's not to say that future applications that are going to be more memory intensive won't see the full benefits of the bandwidth.
(Lost audio due to power failure on event site.)
David Dorrough: (picking up after audio resumption) ...
Joe |
