SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 91.18-4.3%Nov 17 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Bilow who wrote (43166)5/30/2000 3:12:00 AM
From: jim kelley  Read Replies (1) of 93625
 
Carl,

Pale words of praise from a paid basher.
It is curious that those who claim to be in possession of the facts are so prone to drawing the wrong conclusions.<LOL>

Actually the post is my own, I do not copy without attribution.

The "64 bit cache line access" is used many times in other posts. I have not checked its correctness but it does not matter to my argument. If the cache line is 256 bits my argument is stronger. If what you say is correct and the PIII has a 256 bit Cache line, then RDRAM average latency will be that much less than the initial latency. There will be 15 fast transfers and only one slightly slower transfer. This will be generally true although there will be occasional exceptions.

INTEL did not have to create the notion of "average latency." It is an obvious concept. The same will be true for DRAM. As such it is not a "marketing buzz word ".

Of course, the design of Tom's benchmark programs was focused on stressing "initial latency." They did this by using randomizing data references in a large array. This negated RDRAM's superior bandwidth in multiword transfers.
This is what Scumbucket was attempting confuse mom and pop with in his earlier posts. The agenda is clear: Focus people's attention on a situation which is anomalous in computer programs. Programs have a great deal of locality.
Data also has locality. Tom has created exceptions to these two principles. The lie is to say that these are normal conditions.

Obviously, latency and bandwidth are related. If the test programs reduce the word transfer to one then RDRAM wil have a penalty relative to some SDRAM other things being equal. But this is not the normal state of affairs!

As I said before, there is a lot of arrogance and cynicism being displayed in the attempt to confuse. This means there is great fear of RDRAM at AMD. Otherwise, why spend so much energy in this intense game of deception.





Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext