SAN JOSE, Calif.--(BW)--May 31, 2000--To Include Speed-Optimized Embedded DRAM, Analog/Mixed-Signal, Multi-Gigabit SONET and InfiniBand
Fujitsu Microelectronics, Inc. (FMI) today introduced its new 0.11 micron gate length (0.11um Lgate) ASIC process capability, featuring the industry's lowest power, fastest transistors and most compact memory cells.
Fujitsu's 0.11 micron technology (0.07 micron Leff), which will be available by the third quarter of 2001, features shallow trench isolation (STI) techniques, chemical-mechanical polishing (CMP) for all planarization and CoSi2 in transistor gate and source/drain. The all-layer copper-interconnect process uses five to eight levels of metal and low-k (k <= 2.6) dielectric techniques. Initial products developed using the very deep submicron process will support devices with as many as 56 million gates per chip. The gates will be characterized at 0.85V to 1.65V, with analog and I/O blocks to be available in both 2.5V and 3.3V. The junction temperature range is -40(degrees)C to 125(degrees)C. Densities are twice those of ASICs manufactured using Fujitsu's 0.18 micron process technology.
The power requirements for Fujitsu's 0.11 micron process are 2nW/MHz/gate at 1.2V. The technology also features the industry's smallest memory cells, at only 2 micron squared (2 um2) for the 6-transistor SRAM and 0.2 micron squared for embedded DRAM.
"This very deep submicron technology continues Fujitsu's leadership in one of the technologies driving advanced networking and communications design, as well as digital A/V design," said Ryusuke Hoshikawa, FMI's president and chief executive officer and a member of Fujitsu's board of directors. "The new ASIC series and technology provide our customers with extremely fast, high-density products with very high pin counts, along with a large array of cell libraries, macros and IP cores. We will be moving aggressively to bring our initial products to our leading customers in Japan and in North America quickly and efficiently."
CS91/CE91 to be First Product at 0.11 Micron
Fujitsu's first release using the new deep submicron technology will be the high density, low power Standard Cell CS91 and the quick TAT (Turn Around Time) Embedded Array CE91 ASIC series designed for high density, high pin count LSI and portable system LSI. The CS91/CE91 will feature high-performance analog elements, such as ADC, DAC and op amps, along with memory compilers for single- and dual-port SRAM, ROM and Register files. The first design library will be available by the end of this year, with basic gates and initial I/O options, including some memory blocks and mixed-signal macros. The full library release containing the high-performance/speed CS91Z gates, memory compilers, various high-speed I/O interfaces (LVDS, SSTL_2, HSTL, etc.), special purpose I/Os (PCI, graphics, USB and others) is due by the third quarter of 2001. Multi-gigabit interfaces including SONET and InfiniBand will be also available.
Fujitsu also plans an embedded DRAM offering, the CS90DLS, which will provide more than 192 Mb of DRAM for each 100 mm2 area.
Clock frequencies for the embedded DRAM will reach 200 MHz for SDRAM and more than 300 MHz for Fujitsu's FCRAMs (Fast Cycle RAMs). Packaging for the CS91/CE91 series will be in high ball-count and fine ball-pitch flip-chip BGAs.
Jim |
