SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: milo_morai who wrote (114086)6/4/2000 2:28:00 PM
From: Scumbria  Read Replies (2) of 1576372
 
Milo,

Besides integrating the L2, AMD has shifted the cache architecture to an
exclusive cache design. Many of the current generation of processors with on-die
L2, including those from Intel, use an inclusive cache architecture, in which
the entire contents of the Level 1 cache is mirrored in the L2. AMD's approach
does not duplicate the L1, so there is more space to store information in the
L2.

"This is an improvement," said Dean McCarron, principal analyst for Mercury
Research (Scottsdale, Ariz.). While he characterized the use of the exclusive
cache architecture as a small step forward, he said it is more significant than
a simple bump up in speed grades. "This translates to better use of the cache
memory."

Another performance boost will come from increasing the frequency of the
secondary cache. The integrated cache runs at the same speed as the processor
core. The off-die Athlon cache was originally intended to run at half the speed
of the processor. But Bode said off-die cache speeds have reached a ceiling in
the mid-300-MHz range. Chips with processor cores exceeding 700 MHz have
suffered a performance hit because the L2 cache runs at less than half the speed
of the processor core. McCarron said one recently produced 1-GHz Athlon featured
a 350-MHz cache-just a bit better than one-third the speed of the core.


It would be nonsensical to put anything other than exclusive cache on board Athlon. With a 128K L1, a 64K inclusive L2 would be no better than 0K L2.

The topic of full-speed L2 keeps coming up over and over again. The principle value of an onboard-L2 cache is that it provides lower latency than an off-chip cache. The clock speed of the cache is of secondary importance.

Scumbria
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext