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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (114172)6/4/2000 10:54:00 PM
From: Trent George  Read Replies (1) of 1576849
 
There are conflicting specifications for the TBird.
Tom says 112mm^2 up to 1.2GHz and 256bit width L2 Cache bus
Anandtech says 120mm^2 to 1Ghz and 64bit width L2 Cache.

I think they are both guessing !
I think 16 way L2 cache would suggest a smaller L2 cache line (64 bit seems appropriate)

64bit would also be more in line with 64bit sdram and should reduce latency on a cache line fill from RAM, also with exclusive cache (L1 & L2) there will never be a ram to L2 fill but only a L1 > L2 and RAM > L1, right ? 64 bits would make everything go in the same cycle? vs 256 Coppermine does 4 sets of 64 bits into L2 and L1 from SDRAM, delaying things until all 256 bits are in, but speeding things for access to subsequent (now in cache) access?

Any comments from anyone ?
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