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Politics : Formerly About Advanced Micro Devices

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To: Tenchusatsu who wrote (114260)	6/5/2000 2:20:00 AM
From: Cirruslvr	Read Replies (1) of 1575771

Tench - RE: "The 64-bit BSB width is surprising to me. With the "exclusive" L2 cache (a.k.a. Victim Cache), I figure T-bird will need the BSB bandwidth a LOT more than Coppermine because of all the swapping of data between L1 and L2. Maybe AMD will increase the BSB width on Mustang." This means Cumine's L2 cache has double the bandwidth, right? Athlon has 64bit BSB that I assume works at full speed while Cumine has 256bit, but is half speed (or sends every other clock). It would seem to a technically illiterate person like me that since the Athlon has 4X the L1 cache of Cumine, it would need more L2 bandwidth to send the send data. Does that make sense? Whatever the AMD engineers' reasoning to do what they did was, I am sure it made sense. They DID design the Athlon... Does having a wider BSB width have any effect on limiting on clock speed? Maybe AMD engineers didn't want to risk it. Are you more confident about Willy now?

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