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Politics : Formerly About Advanced Micro Devices

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To: Scumbria who wrote (114272)	6/5/2000 3:09:00 AM
From: Tenchusatsu	Read Replies (1) of 1575428

Scumbria, <There is no reason why higher associativity should slow down an onboard L2 cache> If what you're saying is true, then why doesn't AMD just go straight to a fully-associative cache? And why is Athlon's L1 cache only 2-way set-associative? (Hint: It's an oversized cache, so to make up for the slowness of such a large cache, a lower associativity is necessary.) <BSB is an Intel term.> Well, what else am I supposed to call it? Isn't FSB an Intel term as well? <T-Bird does not need as much bandwidth between caches, as PIII. The only really important beat of data is the first one, and a 64 bit bus is more than adequate to fill that need.> But with a victim cache, any L1 eviction will cause a transfer of an entire cacheline from L1 to L2. With 64 bytes per cacheline, it will take eight clocks to transfer that entire line. That's a lot of data to squeeze through. What if multiple L1 lines need to be evicted in a burst? Will the processor wait for all the lines to transfer out of L1 to L2? Perhaps Athlon will just drop some of the lines, but then that kind of defeats the purpose of a victim cache. I don't want to second guess experienced processor architects with many years of experience. Perhaps AMD figured that for any L2 cache less than 512K, a victim cache will work better than a traditional "inclusive" cache. But at least the results speak for themselves: T-bird isn't as fast as many people thought. So what could have been a knockout punch against Pentium III turns out to be just a light jab. Maybe AMD's 760 chipset will finally save the day in the battle between Athlon and Pentium III. But then again, a year ago, would you have ever expected Pentium III to be this close to "seventh-generation technology" from AMD? Tenchusatsu

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