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Politics : Formerly About Advanced Micro Devices

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To: Tenchusatsu who wrote (114292)6/5/2000 3:18:00 AM
From: Scumbria  Read Replies (1) of 1574854
 
Ten,

If what you're saying is true, then why doesn't AMD just go straight to a fully-associative cache? And why is Athlon's L1 cache only 2-way set-associative? (Hint: It's an oversized cache, so to make up for the slowness of such a large cache, a lower associativity is necessary.)

A fully associative 256K cache would require a huge amount of real estate for tag comparators, and would draw as much power as a Merced.

An L1 cache has to do address translation and tag comparison in one or two cycles. An L2 cache has several more cycles to do the tag comparison, and higher associativities need not impact performance.

Hint: You are arguing with the wrong person about cache design ;^)

With 64 bytes per cacheline, it will take eight clocks to transfer that entire line. That's a lot of data to squeeze through. What if multiple L1 lines need to be evicted in a burst? Will the processor wait for all the lines to transfer out of L1 to L2? Perhaps Athlon will just drop some of the lines, but then that kind of defeats the purpose of a victim cache.

Large buffers between the L1 and L2 take care of this.

T-bird isn't as fast as many people thought. So what could have been a knockout punch against Pentium III turns out to be just a light jab.

Current chipsets limit T-Bird speed. A good DDR chipset will probably leave PIII in the dust.

Scumbria
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