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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (114297)6/5/2000 9:18:00 AM
From: Scumbria  Read Replies (1) of 1574678
 
Ten,

So what you are saying here is that L1 needs to do the translation and comparison in one or two cycles, which is why it doesn't have such a high associativity. Isn't that kind of supporting my original point, that a higher associativity translates to a longer L2 latency (including the address translation and tag comparison)?

No, because (unlike an L1 cache) the tag lookup on an onboard L2 cache does not need to be in the critical timing path. It is possible to start the L2 tag lookup only one or two cycles after the L1 tag lookup, and it should complete in a single cycle.

If the T-Bird L2 is really 11 clocks latency, that indicates some other (serious) problem with the design.

Scumbria
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