PMCS Supercomm product announcements
PMC-Sierra: Physical Layer/Framer
PMC-Sierra introduced the CMOS OC-48c Physical Layer/Framer Device. The new S/UNI-2488 OC-48c framer is an all-CMOS physical layer solution that integrates analog clock and data recovery, clock synthesis serializer/deserializer functions with the digital framer.
PMC-Sierra: PM5381 S/UNI-2488
PMC-Sierra announced the PM5381 S/UNI-2488 physical layer/framer device an all-CMOS mixed-signal solution for OC-48c applications. The S/UNI-2488 device integrates the digital framer and processor functions together with analog physical layer front-end clock and data recovery, clock synthesis (CRSU) and serializer/deserializer (SERDES) functions. The low-power, single-chip S/UNI-2488 device provides jitter performance, including jitter transfer compliance. The S/UNI-2488 device also provides a high-speed serial-to-serial and serial-to-parallel dual-mode operation which enables the mass deployment of high-speed routers, multiservice switches and optical cross-connect equipment.
PMC-Sierra: CHESS Chip Set
PMC-Sierra introduced the new OC-48 Chip Set Architecture to enable next-generation optical network deployment. According to the company the CHESS channelized chip set architecture manages and grooms multiservice IP, voice, frame relay and ATM traffic over both SONET/SDH and DWDM transport equipment.
PMC-Sierra: OC-48/OC-48c
PMC-Sierra announced a new OC-48/OC-48c (2.5 Gbit/s) channelized architecture designed to completely revolutionize the way carrier and Internet Service Provider (ISP) networks are built, deployed and managed, the company said. The CHESS (Channelizer Engine for SONET/SDH) chip set will allow for convergence of traditionally separate voice and data infrastructure into new, highly integrated carrier-class multiservice networks. According to the company, the CHESS chip set is a set architecture allowing IP routing, ATM/frame relay switching, SONET/SDH digital cross-connect/add-drop multiplexing and dense wavelength division multiplexing (DWDM) transport functionality to be built in a single, space-efficient hardware platform.
PMC-Sierra: TT1 Chip Set
PMC-Sierra announced the Tiny Tera One (TT1) switching fabric chip set for next-generation, high-speed carrier class equipment. The new chip set features the Line Card to Switch (LCS) protocol to enable scaleable terabit routers, ATM switches and optical switches capable of tens of gigabits per second (Gbit/s) through to tens of terabits per second (Tbit/s) aggregate bandwidth.
The TT1 chip set consists of four chips ? the PM9311 TT1 Scheduler, the PM9312 TT1 Cross Bar, the PM9313 TT1 Data Slice and the PM9315 Enhanced Port Processor. According to the company, this chip set's unique, scaleable architecture provides a single switching platform that supports today's high-speed, mixed-traffic, carrier class networks. The TT1 switching fabric supports line cards with both circuit-switched and packet-switched data traffic such as Internet protocol (IP), packet-over-SONET, ATM and frame relay, in any mix, at rates up to OC-192 (10 Gbit/s).
PMC-Sierra: Comet Quad
PMC-Sierra announced the new four-channel PM4354 COMET-QUAD, a four-channel T1, E1 and J1 framer with integrated analog Line Interface Unit (LIU). The integrated COMET-QUAD joins the 3.3V single chip T1/E1/J1 framer and LIU, the PM4351 COMET. The COMET-QUAD is ideal for applications where board space is at a premium such as Internet and multiservice access equipment, Voice over DSL (VoDSL) and Voice over IP (VoIP) Gateways, Wireless Base Stations and Digital Loop Carrier systems, said the company.
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