DDR Rises
In an impressive showing of unity, representatives from many of the major memory manufacturers along with the Chairman of the influential JEDEC Board of Directors Desi Rhoden, AMD's Chipset Marketing Manager Ron Huff, Transmeta's Bill Gervasi, S3's Michael Buchanan, and Via's President and CEO Wen-chi Chen stood shoulder to shoulder to announce their enthusiastic support for DDR SDRAM, the high bandwidth successor to SDRAM and chief rival to the Rambus-Intel RDRAM proprietary initiative.
Even Samsung, easily the world's leading producer of RDRAM, sent their Director of Technology Enabling, Mian Quddus, who is also Chairman of the Jedec Memory Module Committee, to discuss part of Samsung's role in the DDR SDRAM world in bringing a unified DDR SDRAM gerber standard to the industry. Gerbers are the circuit boards that the DDR SDRAM devices will populate. It is critical to establish an industry standard to ensure rapid deployment of DDR, scheduled to ramp in August. A unified standard also helps ensure that DDR DIMMs from various manufacturers work seamlessly in the same system.
AMD's Ron Huff reiterated that overall memory system latencies will decrease in Athlon systems due to the fact that the memory, chipset and CPU communicate synchronously. In fact, Mr. Huff declared DDR SDRAM memory as the "lowest latency and highest bandwidth PC memory."
Desi Rhoden, also President and CEO of AMI2, made a persuasive presentation positioning DDR SDRAM as a low risk, evolutionary, low power consumption, high performing, royalty free technology. DDR SDRAM will be cheap partially because it is created on the same die as SDRAM, make fabrication simple and involving a minimum amount of retooling. Mr. Rhoden stressed that DDR SDRAM is a simple, evolutionary technology to SDRAM. He mentioned, as he revealed to us at WinHec, the DDR SDRAM can actually reduce system latencies over SDRAM. He also mentioned that DDR SDRAM saves power over SDRAM and is well suited for mobile applications as Tranmeta's Bill Gervasi later reiterated. Laptop DDR SDRAM is currently sampling.
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To further demonstrate the support that DDR SDRAM enjoys, Mr. Rhoden presented a slide showing 17 announced DDR SDRAM chipsets and hinted strongly that there are many other unannounced chipsets waiting in the wings.
The Hyundai representative, Farhad Tabrizi, mentioned that DDR SDRAM is preferable over Rambus RDRAM particularly in servers, partially due to reliability issues. DDR SDRAM is more scalable (current RDRAM offerings are very limited by the number of RIMM slots), and is also more robust in that it can survive "chip kill", a condition where a single device fails, something that RDRAM, due to its serial nature, is vulnerable to. Mr. Tabrizi projected DDR SDRAM bandwidth at 9.6 GB/s in 2001. Stating that it is a matter of pride for Hyundai, an enormous memory manufacturer, that the company is hitting its highest yields per wafer on DDR SDRAM.
Partially due to DDR SDRAM's greatly reduced capacitance, DDR SDRAM consumes around half the power of SDRAM, Mr. Gervasi of Transmeta claimed. This is extremely important to Transmeta as its products are targeted to exploit the portable market where low power consumption is critical.
Mike Seibert from Micron projected an initial 3% price premium for DDR SDRAM modules over SDRAM. In 2001 he predicted a price of $10.15 for an 8Mx16 128 Mb SDRAM ASP and $10.45 for a similar DDR SDRAM device. Mr. Siebert said that the largest expense will be on the motherboard, totaling about $6 mainly for the 2.5V voltage converter.
In an obvious reference to RDRAM and perhaps alluding to Tom's Hardware Guide's recent articles, Gil Russell of Infineon assured the audience that DDR SDRAM will prove its merit by benchmark performance unlike competing technology.
Via's chipsets will be designed to support both SDRAM and DDR SDRAM, Eric Chang of Via disclosed. Additionally, Via's Pro2000 DDR SDRAM chipsets will be made to work with both AMD Athlon and Intel PIII chips, differing only in front side bus (FSB) interface circuitry. The Pro2000 will also implement a fast 266 GB/s point to point "V-Link" bus to the south bridge.
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