John Walliker, <I think you may have missed the whole point of the Rambus interface. It does maintain an essentially constant (high) impedance regardless of whether the device is transmitting or receiving.>
I think you are still doing your theoretical
SPICE modelling of RMAbus, do you? Let me
remind you that the difference between practice
and theory is much bigger in practice than in
theory. Second, look at what you just wrote,
"essentially constant". How "essentially"?
Essentially constant is not constant, and
when you multiply the difference by 30
(devices), you may face some unpleasant reality.
As I noted before, the RAMbus training materials
refer to Rambus signals as "chaos" when the reads
are in progress.
Then, you say: "constant (high) impedance".
High? Huh? Is not it supposed to match the 28 Ohm
trace impedance to avoid reflections I was so
scared of? And if the impedance of driver
is "high" as you say, don't you think there
might be difficulties to drive the 28-Ohm
bus to 1.4V above the reference point if the
whole supply rails are 2.5V only?
Then you say: <That is one reason why it uses
constant current bus drivers>
I would be exited to see anything "constant"
in the 800-MHz timing range. Maybe only in theory?
<The other one is that multiple clock domains can then coexist on the bus>
You probably had in mind "time domains"?
The multiple domains have to coexist if the bus
is longer than the signal propagation time.
No matter where it is - on Rambus premises, or AMD
or Intel board. Even on Mars.
<However, what you wrote perfectly sums up the problems which DDR faces.>
You must be also a pointy-haired just like jim_kelley
is. And you both are very confused.
One more time: the Rambus problem is that
there is too many chips on the bus, so the bus
has to be too long. This is not about DDR in any way.
P.S. The tone of my post was intentionally aggressive,
for the sake of delivering the point to slow members.
Do not feel personally offended:). |
