Dear Tench:
Against Dual Cmine 1Ghz on i840 with 4 256MB PC800 RIMMs, Dual 1.2GHz (4.5 x 266) Tbirds with 2GB of PC2100 plus optimizing compiler for each will show a triple in FPU apps for the Tbird system. If Dual 1.4Ghz, if that, Williamettes on Colusa has 4 RIMMs on 2 channels, it will go against Dual 1.46GHz (5.5 x 266) Mustangs with 2GB of PC2100 still will be faster due to 2 fully pipelined FPU on each versus 1 FPU on Williamette. Also the Willies have to share their FSB and have higher latency smaller memory.
Most of those pins on socket A are not copied as they are power or not used. If you think so, Williamettes 472 pins should also need to be mostly duplicated as well. Less than 150 pins need to be in each channel on socket A. Thus, 300 pins for the two EV-6 channels, 100 pins for DDR memory, 50 for LDT, and say 50 for power monitoring, overhead, etc. This means more like 500 pins exclusive of power or say 600 max. For Colusa, 200 pins for the quad pumped FSB, 40 for each RDRAM channel, 150 for AGP, 150 for PCI, the same 150 for power and overhead adds to 730 pins total. That is larger for Colusa than 760MP. The 760 SB takes the LDT and splits it to AGP, PCI, IDE, Floppy, USB, etc., and this will probably be as large. 760MP are being sampled now, where is Colusa? Another late product?
If Colusa is 1H 2001, it will be against Sledgehammer and its embedded NB with 5 LDTs and 2 DDRDRAM channels. One of the LDTs connect to the SB as before and the others form a matrix to connect as many Sledgehammers as required. Each Sledgehammer will have two independent CPUs, and an embedded NB. It will be able to use 64bit addresses and data, and each CPU's FPUs, 3D-Now ALUs, and Prefetch units will be able to work with the cores flat FP Register Array (about 16 to 32 regs) like any RISC FPU. At that point, Williamette better be 3x faster or there will be angry Intel Stockholders forming a "Lynch Mob".
Pete |
