SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Joe NYC who wrote (115671)6/13/2000 1:23:00 AM
From: THE WATSONYOUTH  Read Replies (1) of 1571926
 
Re: "What do you think the Coppermine-T could be? New revision? A die shrink? Some kind of optimization? It looks like this will be some major revision of the core to
find itself on the roadmap, but not too radical to earn a code name? Is there any room to for the .18u equipment to get to .15u or lower?"

I'll make a guess. Perhaps Intel optimized their 1.65V device a bit further allowing an additional 50A reduction in minimum channel length for an approx 7% improvement. They then combine this with an approx. 10% linear shrink ( about 20% area) to realize perhaps a total 15% speed improvement. This probably allows them a 1.2GHz bin split with minimum effort. They don't change the gate ox. or Vcc so as long as the new minimum device meets all other requirements, (Vt/Ioff/etc.) it's a drop in. A 10 percent linear shrink is
easily achievable with the existing tool set and is likely not large enough to require an adjustment to film
thicknesses. Also, the new device (if always shot small) will not break any ground rules and should fit in to the smaller area. This might be the easiest way to achieve a quick bump to maybe 1.2GHz. I expect Mustang will be a partial shrink as well. The ground rules AMD is using on Athlon and I assume on Thunderbird as well are NOT at all aggressive. In fact, the SRAM cell size is 5.95um2 which is surely larger than Intel even though AMD uses local interconnect which for similar ground rules allows for a 20% smaller cell size and perhaps a 15% increase in logic density. For instance, the SRAM cell in an IBM .18um process is about 4.3um2. So, I expect AMD to use this benefit more to their advantage with Mustang. Perhaps they are being overly conservative with Athlon/Thunderbird.

all speculation
THE WATSONYOUTH
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News