SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Politics : Formerly About Advanced Micro Devices

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (115686)6/13/2000 2:08:00 AM
From: Joe NYC  Read Replies (3) of 1572276
 
Scumbria,

The advantage the BX carries is lots of research into the algorithms used. This can make a huge difference in the ratio of page hits vs. page misses, and thus a large difference in latency.

I agree with that. Plus, the interface was synchronous, vs. all other chips on the market that are asynchronous (except 760 and 750?). I don't know how this would apply to Rambus, but you could think of scheme where the critical word is fed to the CPU (2 bytes at the time) and once there, the CPU could continue to run, even before full 8 bytes are retrieved (as is the case with off chip north bridge)

All that an on-chip memory controller does for you is to reduce latency by a few clocks, so there is less impact on performance.

Well, Rambus may die because of a few clocks of latency. I think the few clocks of latency are going to be very important as the CPU speed go up, and a few clocks of latency of the FSB will translate to several dozen (CPU) clocks of stalled CPU.

Joe
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext