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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (115686)6/13/2000 4:15:00 PM
From: Daniel Schuh  Read Replies (1) of 1572260
 
Scumbria, can you explain a little what you mean by "algorithms used" here? I assume you're talking about managing row buffers and stuff like that in DRAM. I know Rambus has some, er, flexibility there, but I though with conventional DRAM that kind of stuff was pretty much fixed by the order of memory accesses. Are there multiple row buffers?

There is the possibility of interleaving, I didn't think that was done since the early PPro FPM chipsets though. The P5 chipsets managed the external L2 cache, so there was some cache management policy to be done there, but that's long gone. What algorithmic flexibility is there in what a memory controller does these days? (leaving the Rambus can of worms aside, of course).

Cheers, Dan.
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