Startup spins 1-GHz CPU for embedded
RELATED SYMBOLS: (AMD)(JNPR)(CSCO)(IBM)(MIPS)
Jun. 13, 2000 (Electronic Engineering Times - CMP via COMTEX) -- SANTA CLARA,
CALIF. - Startup SiByte Inc. will launch a 64-bit MIPS-based microprocessor
aimed at networking that will hit speeds up to 1 GHz and run on just 2.5 watts.
The company is one of many lining up at this week's Embedded Processor Forum
here to capitalize on the communications boom with innovative microprocessor
designs that rival the performance of the best PC processors.
Indeed, the latest crop of devices indicates the performance race may shift to
embedded architectures, where non-X86 designs are vying to stake out a claim to
communications.
"Our motto is server-class performance in the embedded space," said Dan
Dobberpuhl, founder, CEO and president of SiByte. Dobberpuhl was a key designer
for Digital Equipment Corp. and played important roles in both the Alpha
design-often considered the world's fastest microprocessor-and the StrongARM
chip, one of the most power-efficient architectures in the embedded realm.
SiByte's first core design, the SB-1, is essentially an Alpha-class processor
running at near-StrongARM power levels. The company will detail the core this
week at the forum. It runs at frequencies ranging from 600 MHz to 1 GHz using
the 64-bit MIPS instruction set. With a die size of about 25 mm2, it was
designed for multiprocessor implementations. The first chip based on the
architecture will be aimed at the networking market, where high performance is
taken for granted.
The ascendancy of networking as a technology driver is seen in an abundance of
forum papers describing communications processors. "We're seeing a lot more
activity in the networking space," said Tom Halfhill, embedded processor analyst
for MicroDesign Resources (Sunnyvale, Calif.), who will moderate a panel on
high-performance architectures at the conference.
Those architectures include a MIPS-based design from Lexra Inc., the NetVortex,
and a DSP-based approach from BOPS Inc. called the Manta (see stories, page 18).
MIPS Technologies Inc. will also introduce a 64-bit architecture, the 20K, which
the company said will be the foundation of its high-performance 64-bit product
line for the next several years.
Other anticipated papers will detail designs from configurable-processor vendor
Transmeta Corp., a new PowerPC from IBM Microelectronics and a very-low-power
MIPS-based architecture from Alchemy Semiconductor Inc.
But it may be hard to top the SiByte design. The SB-1 core features a quad-issue
pipeline and offers more than 2,000 Dhrystone Mips. The 1-GHz version runs on
2.5 W, with slower versions using even less power. Dobberpuhl said the core
delivers more than 800 Mips/W. That's "about the same amount of Mips per watt as
the StrongARM design," he noted, "but [with] 10 times the performance of that
architecture."
Dobberpuhl said there is no mathematical or architectural limit to the number of
cores that can be placed on a single die, though analyst Halfhill said he
expected the first few chips will use two or four cores. SiByte plans to sample
its first actual chip based on the core by year's end, with volume shipments to
follow early next year.
With clock rates in the gigahertz range, the core is as powerful as the most
advanced X86 chips from Intel and Advanced Micro Devices, but its power
consumption puts it closer to the Crusoe from Transmeta.
SiByte is not looking at the PC market but at high-end networking. While the
networking bandwidth required in routers and switches continues to swell, power
dissipation is becoming more critical because of the heat levels in systems and
increasingly crowded wiring closets.
The company eventually plans a family of chips based on the SB-1, and promises
to soon roll a less-powerful version aimed at lower-bandwidth networking. By the
end of next year, SiByte says it will bring out a third chip packed with more of
the SB-1 cores and delivering even greater performance.
Dobberpuhl and his team of 90 engineers are starting work on the SB-2, and
several chips based on that core are planned. With an eye toward the
multiprocessing element, SiByte has created a proprietary bus to link the cores
within the die, running at 16 Gbytes/second. It will be used in future
implementations of the architecture.
The SB-1 will be manufactured in a 0.15-micron standard process at one of the
larger foundries. The company declined to name its current foundry partner, but
Dobberpuhl said it will eventually have agreements with more than one
manufacturer and won't be limited to a single supplier.
Dobberpuhl has created one of the biggest MIPS-based design teams in the world,
and they have put together what he claims is the most powerful MIPS design in
the industry. Halfhill said that the SiByte design "goes even further than the
new [64-bit architecture] product from MIPS [itself]."
"Our design is 100 percent MIPS-compatible, which should make it easier for
designers to work with our chips," said Dobberpuhl. "That was an important issue
for us."
Cisco Systems Inc. and Juniper Networks Inc. have taken undisclosed equity
stakes in SiByte and are expected to be early customers. Dobberpuhl stressed
that SiByte will not license the technology but will make and sell the products
itself.
That isn't surprising, considering Dobberpuhl's background. He watched his two
other designs get sold off, with Compaq taking the Alpha and Intel the
StrongARM. He hopes to take SiByte public eventually, and the company will not
be acquired; Dobberpuhl has no plans to let anybody else shepherd his latest
design into the market. "The last thing I want to do is go work for another big
company," he said. "We think we've got a winner here."
eetimes.com
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By: Will Wade
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