Process transition, multicore design and shift to Rambus could determine the winners -- Network processors race toward 10-gigabit goal
Jun. 16, 2000 (Electronic Engineering Times - CMP via COMTEX) -- SAN JOSE,
CALIF. - With several network processors emerging to handle OC-48 bandwidth,
chip makers are turning their sights on OC-192 traffic, which pours in at up to
10 Gbits/second. The first chips at this level will likely ship late next year,
in time for widespread deployment of OC-192 fibers.
The winners in the race to deploy a cost-effective single-chip design for OC-192
must navigate IC process transitions, add more RISC engines and replumb for
higher bandwidth all around. These 10-Gbit/s chips will probably require a shift
to Rambus memory as well.
MMC Networks Inc. (Sunnyvale, Calif.), which originated the network processor
market, opened the jousting by laying out a road map to a 20-Gbit/s chip
(full-duplex OC-192) slated for late 2001. MMC is even claiming that other
vendors will have problems scaling their architectures to match that performance
level.
That company, along with Intel, Sitera (now part of Vitesse) and Agere (now part
of Lucent Technologies), appears to have the most headroom in its current
designs. All four should be able to deliver OC-192 network processors by the end
of next year if they can execute well.
New entrant Lexra Inc. (Waltham, Mass.) also plans to ship an OC-192 network
processor in late 2001. Meanwhile, IBM and C-Port-now a subsidiary of
Motorola-have more design work to do before deploying single-chip OC-192
products.
The easiest way for network processor vendors to increase their performance is
to add more RISC engines. The task of processing packets is inherently parallel,
making it easy to share among many processor cores. Each core can work on a
different packet, and in a high-speed router, there are plenty of packets to go
around.
Adding cores is fairly easy. They are physically quite small, typically just a
few square millimeters in an 0.18-micron CMOS process. At that size, vendors can
pack 16 or more onto a modest-size die. Since all the cores on a particular chip
are generally identical, adding more requires little design effort, although the
bandwidth of the on-chip buses must be increased accordingly. Connecting more
than a handful of cores generally requires an internal crossbar or switch rather
than a single bus.
Revving the engines
From that perspective, Intel, Vitesse and MMC will have an easier time
increasing their performance, since they use relatively few RISC engines now.
For example, Intel's IXP1200 is built in an aging 0.28-micron fab acquired from
Digital Equipment Corp. By moving the part to its 0.18-micron process, Intel
could easily pack 16 RISC engines onto the die while maintaining the same cost
structure as the current six-cylinder part.
Simply shoveling in more cores is good only to a point. IBM and C-Port already
pack 16 RISC engines into their high-end network processors. Scaling much beyond
that level stretches the bounds of an 0.18-micron process. Furthermore, with 16
or more cores, just connecting the cores consumes a significant part of the die
area.
An alternative is to increase the clock speed of the RISC engines. A faster
clock allows each core to handle more packets, keeping the number of cores in
the processor to a more manageable level. It also reduces the latency of each
packet through the processor. For those reasons, network processor vendors are
looking to crank up their clock speeds.
For vendors using older IC processes, the solution can be as easy as a process
shrink. For example, Intel should be able to push the IXP1200 from 200 to 400
MHz by moving to 0.18 micron. Vitesse Semiconductor Corp. (Camarillo, Calif.)
should be able to match that speed by moving its Prism IQ2000 to a 0.15-micron
process.
Agere Inc. (Austin, Texas) believes it has plenty of headroom in its two-chip
solution: the fast pattern processor (FPP) and router switch processor (RSP)
chips. The initial products, due to ship this year, use a standard-cell design
with a 133-MHz target clock speed. A more customized design in an 0.18-micron
process could see a 50 percent speedup.
Pedal to the metal
Lexra is already pushing the speedometer: At last week's Embedded Processor
Forum, the company disclosed that its NetVortex processor will reach 427 MHz in
a 0.15-micron process. The company is confident of achieving OC-192 performance
at this speed.
In addition to the 10 Gbits/s of line bandwidth needed for an OC-192 port, a
network processor must have adequate bandwidth in other areas as well. In
general, the bandwidth to the switch fabric should match or exceed the line
bandwidth, since nearly all the traffic from one port will be routed to another
port.
IBM, Vitesse and MMC supply switch-fabric chips for their net processors. MMC
has already announced plans for a 320-Gbit/s switch-fabric chip that will
support several OC-192 lines in a single chassis. C-Port claims compatibility
with a variety of third-party switch fabrics, including those from IBM and
PowerX. To simplify this effort, the Common Switch Interface (CSIX) consortium
is developing a standard switch-fabric interface. Vitesse/Sitera, IBM, MMC and
C-Port are all CSIX members.
Memory bandwidth must also scale, as more packet data must be moved into and out
of DRAM. As a rule, a network processor memory subsystem should be able to
sustain at least twice the packet bandwidth, since most packets will be stored
into a DRAM queue and read back later. To allow for other DRAM accesses and for
the inefficiencies of synchronous DRAM, current network processors have three to
four times as much peak DRAM bandwidth as packet bandwidth.
By this rule of thumb, a full-duplex OC-192 processor should sustain at least 5
Gbytes/s (40 Gbits/s) to DRAM. Because double-data-rate SDRAM is less efficient
than standard SDRAM, even a 256-bit-wide DDR memory at 266 MHz would not reach
this level. Not only would such a wide interface require more than 500 pins, it
would be difficult to support less than 256 Mbits using standard dual in-line
memory modules.
Thus, most OC-192 processors are likely to move to Rambus. Four 800-MHz RDRAM
channels can sustain 5 Gbytes/s using only about 200 pins, making it possible to
use as little as 64 Mbits of memory. Other emerging DRAM technologies, such as
FCRAM, may also be used.
In this regard, Vitesse is ahead of the game by integrating an RDRAM controller
on its IQ2000. Most other devices are using PC100 SDRAM to reduce cost, while
IBM's Rainier net processor supports 200-MHz DDR SDRAM. These other vendors will
have to spend more design time integrating RDRAM in their future devices,
although IBM appears willing to accept the larger pin counts required by SDRAM.
Putting it all together
MMC will deliver a multichip OC-192 solution by mid-2001, followed by a
single-chip design in late 2001, said director of marketing Robin Melnick. These
chips will use the same RISC engines as the recently announced nP7120, MMC's
third-generation net processor. The single-chip product will use six RISC
engines, three times as many as the nP7120. To meet the processing requirements
for OC-192, MMC will also boost the clock speed to about 300 MHz by converting
from a semicustom layout to a more optimized design.
Intel will not comment on its plans, but the IXP should make OC-192 speeds by
moving from its antiquated 0.28-micron process to the 0.18-micron process the
company uses for its PC processors. In a more-advanced process, a new IXP chip
could contain 16 RISC engines instead of six and run at 400 MHz or better. This
second-generation device is likely to appear by the second half of 2001.
Like the IXP1200, Vitesse's IQ2000 is designed for gigabit data streams, and two
Vitesse chips are required for full-duplex OC-48. With only four RISC engines,
the IQ2000 appears underpowered, but the chip is able to match Intel's
performance through better load balancing and a more-efficient core design.
Stephen Sheafor, chief technology officer at Sitera Inc. (Longmont, Colo.), said
that Vitesse's next-generation design will leap from a modest 0.25-micron
process to a leading-edge 0.15- or 0.13-micron process. With a more-advanced
process, the company could easily double the current clock speed and move to 12
or 16 cores, reaching the performance needed for OC-192.
For its part, IBM's Rainier was designed with OC-192 in mind, as it is somewhat
overengineered for OC-42 applications, according to chief architect Chuck
Sannipoli. For example, Rainier is designed for up to 8 Gbits/s of line
bandwidth, well beyond what other network processors can handle.
But since Rainier is already in an 0.18-micron process, boosting the clock speed
or adding more RISC engines won't be easy. IBM is relying on a shrink to
0.13-micron CMOS to boost the clock speed of the current device to 200 MHz or
so. To deliver a full-duplex OC-192 solution, the company will pair two of these
chips, one for upstream and one for downstream. This approach, however, will put
IBM at a cost disadvantage compared with single-chip OC-192 solutions.
Most horsepower
With 16 RISC engines, C-Port's C-5 has the most CPU power of today's crop of net
processors. The company expects clock-speed improvements in the future, but
extending the current architecture to full-duplex OC-192 would require 32 RISC
engines at 400 MHz, which is not achievable even in a 0.13-micron process.
Instead, C-Port is working on a new device, known as the C-Y, to reach that
level. Dave Husak, C-Port's chief technology officer, noted that because the C-5
is programmed in a high-level language, it could use a different
microarchitecture while maintaining software compatibility through
recompilation. A more-powerful RISC engine would make a 20-Gbit/s chip easier to
build. Given the extent of the redesign, however, the C-Y may not be available
until 2002.
Agere believes its novel approach (see story, page 26) makes its FPP/RSP
combination more easily scalable than competing devices. Instead of RISC
engines, Agere uses more-powerful specialized compute engines, each handling a
different task, and processes packets in a pipeline rather than in parallel.
Thus, Agere has left it to future products to exploit packet parallelism.
Agere can reach OC-192 performance by simply setting up a second, parallel
packet pipeline and raising its clock speed to 266 MHz. That speed should be
achievable by a full-custom 0.18-micron version of the current standard-cell
0.25-micron design.
For its part, Lexra is a relative latecomer to this market, but it plans to
deliver a 16-core version of its NetVortex processor by late 2001. At 427 MHz,
this 0.15-micron chip will support full-duplex OC-192, claims chief executive
officer Charlie Cheng. Because Lexra is licensing the core design, its licensees
must grapple with the hard problems of supporting enough memory and fabric
bandwidth to handle two OC-192 data streams.
MMC already counts Cisco, 3Com and Nortel among its customers. As a pioneer, MMC
has had this market almost to itself, but competition is now intense, and most
other network processor vendors are now backed by large semiconductor companies.
Intel is making a big thrust into networking, spending more than $2 billion to
acquire Level One Communications and other network chip companies. That figure
doesn't even count the $625 million spent on Digital Semiconductor, which
supplied both the design and the fab for the IXP1200. When Intel makes
investments of this size, it expects a sizable return.
The company claims to have 25 design wins for the IXP1200, including Nortel,
Ericsson and Newbridge. The part is not as sophisticated as some of its
competitors, but it is well-suited to gigabit data streams. With an OC-192 part
looking quite doable, Intel stands poised to carve out a big chunk of this
market.
IBM is the only major semiconductor vendor attacking the market with homegrown
technology. In fact, the company has already developed a low-end chip, dubbed
Charm, to complement Rainier, as well as a 28-Gbit/s switch-fabric chip to
connect up to eight of its network processors.
Most high-end networking products still use custom ASICs, and IBM is the leading
supplier of these ASICs. Thus, the company has already established a channel for
its network processors and switch fabric. This broad product line has attracted
several customers to Rainier, including Nortel, Alcatel and Asante.
C-Port, meanwhile, is integrating its application programming interfaces and
development environment with its parent company's. Motorola plans to deploy a
single tool set to allow customers to write C or C++ programs that run on either
C-Port processors or Motorola's standard PowerPC and PowerQuicc devices.
This broad product line and reliance on high-level programming should help the
C-5 become widely used; the company already claims 20 design wins, including
three top-tier vendors. Because of the significant redesign, however, C-Port's
single-chip OC-192 solution is likely to arrive later than those from other
vendors.
Control edge
Lexra's licensing strategy and ability to execute MIPS instructions give it two
significant differentiators. The largest network-equipment vendors, such as
Cisco and Nortel, are often hesitant to rely on a third party to deliver a key
component without a second source. They also don't want to see other networking
vendors using the same chips to deliver similar products. Lexra allows licensees
to design their own custom components and select their own foundries, giving
these giant vendors more control over their own destiny.
By acquiring Sitera, meanwhile, Vitesse added a network processor to its
portfolio of physical-layer (PHY) chips and switch fabrics. But as a sugar
daddy, Vitesse is not as sweet as Intel, and it lacks the networking ties of IBM
and Motorola. Other than its Rambus interface, Vitesse's IQ2000 has little to
distinguish itself from the competition. The company claims design wins at
Quarry Technologies and Nortel, a promiscuous networking vendor that seems to be
on everyone's customer list.
Now part of Lucent, Agere offers a solid OC-48 solution that should scale well
to OC-192. The FPP-RSP two-chip set, however, is more expensive than any of the
single-chip solutions. Agere claims the requisite 20 design wins, but it remains
to be seen whether Lucent has the muscle to push Agere's product into a crowded
marketplace.
By the end of this year, six vendors are slated to ship network processors
delivering 2-Gbit or better performance. By the end of next year, several will
be shipping 20-Gbit network processors. As more of these devices become
available, they will turn the tide away from the hardwired ASICs that dominate
high-end networking today.
"ASIC designers are always under fire from the software developers" who need the
hardware to validate their code, said Steve Fu, technology partnership manager
of Cisco Systems' enterprise router division. He pointed out that programmable
parts improve time-to-market by allowing software to be tested earlier in the
cycle.
Network-equipment makers evaluating the current processor choices should first
consider performance: Intel's IXP1200 and Vitesse's IQ2000 are best-suited for
dual gigabit or single OC-48 streams, while the others can handle dual OC-48
channels. If price is a concern, MMC is the leader, whereas Agere's two-chip
solution seems overpriced.
Another major criterion is whether to program in a high-level language, which
reduces development time, or in assembly code, which is more compact. C-Port
appears to have the best compiler today, while Lexra will have strong tools
support for its MIPS-based processors. Some may be concerned that Intel is the
only company in the industry that is not supporting industry efforts, under the
Common Processor Interface consortium, to standardize APIs.
Many OEMs prefer to ensure compatibility by obtaining their components from the
same vendor. From this angle, IBM comes out on top. It has the broadest line of
network processors, switch fabrics, control processors and (through its
partnership with Multilink) PHY chips.
With several vendors in the processor market, networking companies have a range
of innovative products to choose from, and prices should be reasonably low. No
net processor vendor is likely to dominate. This competition should spur
increased adoption of network processors.
LINLEY GWENNAP IS THE FOUND-ER AND PRINCIPAL ANALYST OF THE LINLEY GROUP
(WWW.LINLEYGROUP.COM), A TECHNOLOGY ANALYSIS FIRM BASED IN MOUNTAIN VIEW, CALIF.
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