Synchronous semiconductor memory device
Abstract
To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.
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Inventors: Iwamoto; Hisashi (Hyogo, JP); Konishi; Yasuhiro (Hyogo, JP); Dosaka; Katsumi (Hyogo, JP); Murai; Yasumitsu (Hyogo, JP)
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.: 548285
Filed: October 25, 1995
U.S. Class: 365/233; 365/230.03; 365/189.01
Intern'l Class: G11C 007/00
Field of Search: 365/233,230.03,230.01,189.01
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References Cited [Referenced By]
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U.S. Patent Documents
5471430 Nov., 1995 Sawada et al. 365/233.
5517462 May., 1996 Iwamoto et al. 365/233.
Other References
"250 Mbyte/sec Synchronous DRAM Using a 3-State-Pipelined Architecture" Takai et al., '93 Symp. on VLSI circuit pp. 59-60.
"16 Mbit Synchronous DRAM with 125 Mbyte/sec Data Rate" Choi et al., 93 Symp. on VLSI circuit pp. 65-66.
"A 150-MHz-4-Bank 64 M-bit SDRAM with Address Incrementing Pipeline Scheme" Kodama et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers pp. 81-82.
Primary Examiner: Nelms; David C.
Assistant Examiner: Le; Vu A.
Attorney, Agent or Firm: Lowe, Price, LeBlanc & Becker
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Claims
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1. A synchronous semiconductor memory device strobing an external signal including a control signal, an address signal, and a data signal in response to an external clock signal, comprising:
a memory array including a plurality of memory cells arranged in rows and columns;
first and second signal input/output line pairs for inputting/outputting the data signal to and from said memory array;
a frequency division circuit frequency-dividing said external clock signal and outputting an internal clock signal having a period a plurality of times that of the external clock signal;
a selection circuit continuously selecting any memory cell of said memory array according to said address signal;
a switching circuit responsive to said internal clock signal outputted from said frequency division circuit for connecting each of the memory cells selected by said selection circuit to one ends of said first and second signal input/output line pairs alternately on a clock cycle basis; and
a data input/output circuit responsive to said internal clock signal outputted from said frequency division circuit for receiving and transmitting the data signal to and from the other ends of said first and second signal input/output terminal pairs alternately on a clock cycle basis.
2. The synchronous semiconductor memory device according to claim 1, wherein
said data input/output circuit includes
a data reading circuit provided in common to said first and second signal input/output line pairs,
a first switching circuit responsive to said internal clock signal for connecting the other ends of said first and second signal input/output line pairs to said data reading circuit alternately on a clock cycle basis,
a data writing circuit provided in common to said first and second signal input/output line pairs,
a second switching circuit responsive to said internal clock signal for connecting the other ends of said first and second signal input/output line pairs to said data writing circuit alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
3. The synchronous semiconductor memory device according to claim 1, wherein
said data input/output circuit includes
a first data reading circuit provided corresponding to said first signal input/output line pair,
a second data reading circuit provided corresponding to said second signal input/output line pair,
a first switching circuit responsive to said internal clock signal for outputting externally data signals read out by said first and second data reading circuits alternately on a clock cycle basis,
a first data writing circuit provided corresponding to said first signal input/output line pair,
a second data writing circuit provided corresponding to said second signal input/output line pair,
a second switching circuit responsive to said internal clock signal for externally inputting data signals to said first and second data writing circuits alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
4. A synchronous semiconductor memory device strobing an external signal including a control signal, an address signal, and a data signal in synchronization with an external clock signal, comprising:
a memory array including a plurality of memory cells arranged in rows and columns;
first and second signal input/output line pairs for inputting and outputting the data signal to and from said memory array;
a selection circuit continuously selecting any memory cell pair of said memory array according to said address signal;
a connection circuit connecting each of the memory cell pairs selected by said selection circuit to one ends of said first and second signal input/output line pairs; and
a data input/output circuit transmitting and receiving data signals of two bits to and from the other ends of said first and second signal input/output line pairs at a time in the first two clock cycles, and transmitting and receiving a data signal of one bit to and from the other ends of said first and second signal input/output line pairs alternately on a clock cycle basis thereafter.
5. The synchronous semiconductor memory device according to claim 4, wherein
said data input/output circuit includes
a first data reading circuit provided corresponding to said first signal input/output line pair,
a second data reading circuit provided corresponding to said second signal input/output line pair,
a first switching circuit for externally outputting data signals read out by said first and second data reading circuits alternately on a clock cycle basis,
a first data writing circuit provided corresponding to said first signal input/output line pair,
a second data writing circuit provided corresponding to said second signal input/output line pair,
a second switching circuit for externally inputting a data signal to said first and second data writing circuits alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second signal input/output line pairs, and
a writing control circuit equalizing said first and second signal input/output line pairs by said equalize circuit after writing of said data signals of two bits by said first and second data writing circuits in said first two clock cycles, and equalizing said first and second signal input/output line pairs by said equalize circuit after writing of said data signal of one bit by said first or second data writing circuit in each one clock cycle thereafter.
6. A synchronous semiconductor memory device strobing an external signal including a control signal, an address signal, and a data signal in synchronization with an external clock signal, comprising:
a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns, a word line provided corresponding to each row, and a bit line pair provided corresponding to each column;
first and second local signal input/output line pairs provided corresponding to each of said plurality of memory array blocks;
first and second global signal input/output line pairs provided in common to said plurality of memory array blocks;
a frequency division circuit frequency-dividing said external clock signal and outputting an internal clock signal having a frequency a plurality of times that of the external clock signal;
a selection circuit continuously selecting any memory array block of said plurality of memory array blocks and any memory cell belonging to the memory array block according to said address signal;
a switching circuit responsive to said internal clock signal outputted from said frequency division circuit for connecting each of bit line pairs corresponding to the memory cells selected by said selection circuit to one ends of the first and second local signal input/output line pairs of a memory array block to which each bit line pair belongs alternately on a clock cycle basis;
a connection circuit connecting each of the other ends of the first and second local signal input/output line pairs of said memory array blocks selected by said selection circuit to said first and second global signal input/output line pairs; and
a data input/output circuit responsive to said internal clock signal outputted from said frequency division circuit for transmitting and receiving the data signal to and from the other ends of said first and second global signal input/output line pairs alternately on a clock cycle basis.
7. The synchronous semiconductor memory device according to claim 6, wherein
said data input/output circuit includes
a data reading circuit provided in common to said first and second global signal input/output line pairs,
a first switching circuit responsive to said internal clock signal for connecting the other ends of said first and second global signal input/output line pairs to said data reading circuit alternately on a clock cycle basis,
a data writing circuit connected in common to said first and second global signal input/output line pairs,
a second switching circuit responsive to said internal clock signal for connecting the other ends of said first and second global signal input/output line pairs to said data writing circuit alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second global signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first global signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
8. The synchronous semiconductor memory device according to claim 6, wherein
said data input/output circuit includes
a first data reading circuit provided corresponding to said first global signal input/output line pair,
a second data reading circuit provided corresponding to said second global signal input/output line pair,
a first switching circuit responsive to said internal clock signal for externally outputting data signals read out by said first and second data reading circuits alternately on a clock cycle basis,
a first data writing circuit provided corresponding to said first global signal input/output line pair,
a second data writing circuit provided corresponding to said second global signal input/output line pair,
a second switching circuit responsive to said internal clock signal for externally inputting a data signal to said first and second data writing circuits alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second global signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first global signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
9. The synchronous semiconductor memory device according to claim 6, wherein
each of said plurality of memory array blocks includes
a plurality of word line shunt regions provided crossing said word line with a predetermined interval with each other, and
a conductive line of a low resistance provided corresponding to each word line and connected to a corresponding word line in each word line shunt region, and
said first and second global signal input/output line pairs are provided so as to longitudinally cross the word line shunt regions of at least one of said plurality of memory array blocks.
10. The synchronous semiconductor memory device according to claim 9, wherein
said first and second global signal input/output line pairs are provided so as to longitudinally cross different word line shunt regions from each other.
11. A synchronous semiconductor memory device strobing an external signal including a control signal, an address signal, and a data signal in synchronization with an external clock signal, comprising:
a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns, a word line provided corresponding to each row, and a bit line pair provided corresponding to each column;
a local signal input/output line pair provided corresponding to each of said plurality of memory array blocks;
first and second global signal input/output line pairs provided in common to said plurality of memory array blocks;
a frequency division circuit frequency-dividing said external clock signal and outputting an internal clock signal having a period a plurality of times that of the external clock signal;
a selection circuit continuously selecting any memory array block of said plurality of memory array blocks and any memory cell belonging to the memory array block according to said address signal;
a connection circuit connecting each of bit line pairs corresponding to said memory cells selected by said selection circuit to one end of the local signal input/output line pair of a memory array block to which the bit line pair belongs;
a switching circuit responsive to said internal clock signal outputted from said frequency division circuit for connecting each of the other ends of the local signal input/output line pairs of said memory array blocks selected by said selection circuit to one ends of said first and second global signal input/output line pairs alternately on a clock cycle basis; and
a data input/output circuit responsive to said internal clock signal outputted from said frequency division circuit for transmitting and receiving a data signal to and from the other ends of said first and second global signal input/output line pairs alternately on a clock cycle basis.
12. The synchronous semiconductor memory device according to claim 11, wherein
said data input/output circuit includes
a data reading circuit provided in common to said first and second global signal input/output line pairs,
a first switching circuit responsive to said internal clock signal for connecting the other ends of said first and second global signal input/output line pairs to said data reading circuit alternately on a clock cycle basis,
a data writing circuit provided in common to said first and second global signal input/output line pairs,
a second switching circuit responsive to said internal clock signal for connecting the other ends of said first and second global signal input/output line pairs to said data writing circuit alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second global signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first global signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
13. The synchronous semiconductor memory device according to claim 11, wherein
said data input/output circuit includes
a first data reading circuit provided corresponding to said first global signal input/output line pair,
a second data reading circuit provided corresponding to said second global signal input/output line pair,
a first switching circuit responsive to said internal clock signal for externally outputting data signals read out by said first and second data reading circuits alternately on a clock cycle basis,
a first data writing circuit provided corresponding to said first global signal input/output line pair,
a second data writing circuit provided corresponding to said second global signal input/output line pair,
a second switching circuit responsive to said internal clock signal for externally inputting a data signal to said first and second data writing circuits alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second global signal input/output line pairs, and
a third switching circuit responsive to said internal clock signal for connecting the other ends of said second and first global signal input/output line pairs to said equalize circuit alternately on a clock cycle basis.
14. The synchronous semiconductor memory device according to claim 11, wherein
each of said plurality of memory array blocks includes
a plurality of word line shunt regions provided crossing said word line with a predetermined interval with each other, and
a conductive line of a low resistance provided corresponding to each word line and connected to a corresponding word line in each word line shunt region, and
said first and second global signal input/output line pairs are provided so as to longitudinally cross word line shunt regions of at least one of said plurality of memory array blocks.
15. The synchronous semiconductor memory device according to claim 14, wherein
said first and second global signal input/output line pairs are provided so as to longitudinally cross different word line shunt regions from each other.
16. A synchronous semiconductor memory device strobing an external signal including a control signal, an address signal, and a data signal in synchronization with an external clock signal, comprising:
a plurality of memory array blocks each including a plurality of memory cells arranged in rows and columns, a word line provided corresponding to each row, and a bit line pair provided corresponding to each column;
first and second local signal input/output line pairs provided corresponding to each of said plurality of memory array blocks;
first and second global signal input/output line pairs provided in common to said plurality of memory array blocks;
a selection circuit continuously selecting any memory array block of said plurality of memory array blocks and any memory cell pair belonging to the memory array block according to said address signal;
a first connection circuit connecting each of two bit line pairs corresponding to the memory cell pairs selected by said selection circuit to one ends of the first and second local signal input/output line pairs of a memory array block to which the two bit line pairs belong;
a second connection circuit connecting each of the other ends of the first and second local signal input/output line pairs of said memory array blocks selected by said selection circuit to one ends of said first and second global signal input/output line pairs on a two-clock-cycle basis; and
a data input/output circuit transmitting and receiving data signals of two bits to and from the other ends of said first and second global signal input/output line pairs at a time in the first two clock cycles, and transmitting and receiving a data signal of one bit to and from the other ends of said first and second global signal input/output line pairs alternately on a clock cycle basis thereafter.
17. The synchronous semiconductor memory device according to claim 16, wherein
said data input/output circuit includes
a first data reading circuit provided corresponding to said first global signal input/output line pair,
a second data reading circuit provided corresponding to said second global signal input/output line pair,
a first switching circuit for externally outputting data signals read out by said first and second data reading circuits alternately on a clock cycle basis,
a first data writing circuit provided corresponding to said first global signal input/output line pair,
a second data wiring circuit provided corresponding to said second global signal input/output line pair,
a second switching circuit for externally inputting a data signal to said first and second data writing circuits alternately on a clock cycle basis,
an equalize circuit provided in common to said first and second global signal input/output line pairs, and
a writing control circuit equalizing said first and second global signal input/output line pairs by said equalize circuit after writing of said data signals of two bits by said first and second data writing circuits in said first two clock cycles, and equalizing said first and second global signal input/output line pairs by said equalize circuit after writing of said data signal of one bit by said first or second data writing circuit in each one clock cycle thereafter.
18. The synchronous semiconductor memory device according to claim 16, wherein
each of said plurality of memory array blocks includes
a plurality of word line shunt regions provided crossing said word line with a predetermined interval with each other, and
a conductive line of a low resistance provided corresponding to each word line and connected to a corresponding word line in each word line shunt region, and
said first and second global signal input/output line pairs are provided so as to longitudinally cross word line shunt regions of at least one of said plurality of memory array blocks.
19. The synchronous semiconductor memory device according to claim 18, wherein
said first and second global signal input/output line pairs are provided so as to longitudinally cross different word line shunt regions from each other.
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Description
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device which strobes external signals including a control signal, an address signal and a data signal in synchronization with an external clock signal.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as a "DRAM") which is employed as a main memory cannot follow a microprocessor (hereinafter referred to as an "MPU") in operating speed although its operation has been speeded up. Therefore, it is frequently pointed out that an access time and a cycle time of such a DRAM bottleneck the operation of the overall system, to deteriorate its performance. It has been proposed in recent years to employ as a main memory for a high speed MPU a synchronous DRAM (hereinafter referred to as an "SDRAM") which operates in synchronization with a clock signal. Takai et al. read a paper on an SDRAM of pipeline operation carrying out writing of data on a bit basis (Symposium on VLSI circuit, 1993), and Choi et al. read a paper on an SDRAM of 2-bit prefetch carrying out writing of data on a 2-bit basis (Symposium on VLSI circuit, 1993). Description will be given hereinafter of the SDRAM of pipeline operation and the SDRAM of 2-bit prefetch.
FIG. 19 is a block diagram functionally showing a structure of a main part in a conventional SDRAM of pipeline operation. FIG. 19 shows a structure of a functional portion which is related to 1-bit data input/output of the SDRAM having a by 8-bit structure. An array part which is related to a data input/output terminal DQi includes memory arrays 51a and 51b forming banks #1 and #2 respectively.
With respect to memory array 51a forming bank #1, there is provided an X decoder group 52a including a plurality of row decoders for decoding address signals X0 to Xj and selecting a corresponding row of memory array 51a, a Y decoder group 53a including a plurality of column decoders for decoding column address signals Y3 to Yk and generating column selection signals selecting corresponding columns of memory array 51a, and a sense amplifier group 54a for detecting and amplifying data of memory cells which are connected to the selected row of memory array 51a.
X decoder group 52a includes the row decoders which are provided in correspondence to respective word lines of memory array 51a. Row decoders are selected in accordance with address signals X0 to Xj, so that the word lines provided for the selected row decoders are selected.
Y decoder group 53a includes the column decoders which are provided for the respective column selection lines of memory array 51a. A single column selection line brings eight pairs of bit lines into selected states. X decoder group 52a and Y decoder group 53a simultaneously bring 8-bit memory cells into selected states in memory array 51a. X decoder group 52a and Y decoder group 53a are both activated by a bank specifying signal B1.
Bank #1 is further provided with a bus GIO as internal data transmission lines (global IO lines) for transmitting data which are detected and amplified by sense amplifier group 54a and transmitting write data to selected memory cells of memory array 51a. Global IO line bus GIO includes eight pairs of global IO lines for simultaneously transferring and receiving data to and from simultaneously selected 8-bit memory cells.
In order to read data, bank #1 is provided with a preamplifier group 55a which is activated in response to a preamplifier activation signal .phi.PA1 for amplifying data on global IO line bus GIO, a read register 56a for storing data amplified in preamplifier group 55a, and an output buffer 57a for successively outputting the data stored in read register 56a.
Each of preamplifier group 55a and read register 56a has a structure of an 8-bit width in correspondence to the eight pairs of global IO lines. Read register 56a latches the data outputted from preamplifier group 55a to successively output the same in response to a register activation signal .phi.Rr1.
Output buffer 57a transmits the 8-bit data successively outputted from read register 56a to data input/output terminal DQi in response to an output enable signal .phi.OE1. Referring to FIG. 19, data input/output terminal DQi is adapted to input and output the data. Alternatively, the data may be inputted and outputted through separate terminals.
In order to write data, on the other hand, bank #1 is further provided with an input buffer 58a of a 1-bit width which is activated in response to an input buffer activation signal .phi.DB1 for generating internal write data from input data supplied to data input/output terminal DQi, a write register 59a which is activated in response to a register activation signal .phi.Rw1 for successively storing write data received from input buffer 58a (in accordance with wrap addresses), a write buffer group 60a which is activated in response to a write buffer activation signal .phi.WB1 for amplifying and transmitting the data stored in write register 59a to global IO line bus GIO, and an equalize circuit group 61a equalizing global IO line pair bus G10.
Each of write buffer group 60a and write register 59a has an 8-bit width.
Similarly to the above, bank #2 includes memory array 51b, an X decoder group 52b, a Y decoder group 53b, a sense amplifier group 54b which is activated in response to a sense amplifier activation signal .phi.SA2, a preamplifier group 55b which is activated in response to a preamplifier activation signal .phi.PA2, a read register 56b which is activated in response to a register activation signal .phi.Rr2, an output buffer 57b which is activated in response to an output enable signal .phi.OE2, an equalize circuit group 61b which is activated in response to an equalize circuit activation signal .phi.EQ2, a write buffer group 60b which is activated in response to a buffer activation signal .phi.WB2, a write register 59b which is activated in response to a register activation signal .phi.Rw2, and an input buffer 58b which is activated in response to a buffer activation signal .phi.DB2.
Banks #1 and #2 are identical in structure to each other. Due to read registers 56a and 56b and write registers 59a and 59b, it is possible to input/output data in synchronization with a high-speed clock signal through a single data input/output terminal DQi.
As to control signals for banks #1 and #2, only those for either bank are generated in accordance with a bank specifying signal B1 or B2.
A functional block 300 shown in FIG. 19 is provided for each data input/output terminal. The SDRAM of the by 8-bit structure includes eight such functional blocks 300.
Since banks #1 and #2 are substantially identical in structure to each other, it is possible to drive banks #1 and #2 substantially independently of each other by activating only one of these banks by bank specifying signal B1 or B2.
Further, banks #1 and #2 are respectively provided with data read registers 56a and 56b and data write registers 59a and 59b independently of each other, whereby it is possible to correctly read and write data with no collision in switching between data read and write operation modes as well as in switching between banks #1 and #2.
First and second control signal generation circuits 62 and 63 and a clock counter 64 are provided as control systems for independently driving banks #1 and #2 respectively.
First control signal generation circuit 62 takes in externally applied control signals, i.e., an external row address strobe signal ext./RAS ("1" before reference characters indicating signals indicates that the signal is active at a low level in the specification and the drawings), an external column address strobe signal ext./CAS, an external output enable signal ext./OE, an external write enable signal (write authorization signal) ext./WE and a mask command signal WM in synchronization with an external clock signal CLK which is a system clock, for example, to generate internal control signals .phi.xa, .phi.ya, .phi.W, .phi.O, .phi.R and .phi.C.
Second control signal generation circuit 63 generates control signals for independently driving banks #1 and #2 respectively, i.e., equalize circuit activation signals .phi.EQ1 and .phi.EQ2, sense amplifier activation signals .phi.SA1 and .phi.SA2, preamplifier activation signals .phi.PA1 and .phi.PA2, write buffer activation signals .phi.WB1 and .phi.WB2, input buffer activation signals .phi.DB1 and .phi.DB2, and output buffer activation signals .phi.OE1 and .phi.OE2 in response to bank specifying signals B1 and B2, internal control signals .phi.W, .phi.O, .phi.R and .phi.C, and the output of clock counter 64.
The SDRAM further includes, as peripheral circuits, an X address buffer 65 which takes in external address signals ext./A0 to ext./Ai in response to internal control signal .phi.xa to generate internal address signals X0 to Xj and bank selection signals B1 and B2, a Y address buffer 66 which is activated in response to internal control signal .phi.ya for generating column selection signals Y3 to Yk for specifying column selection lines, wrap address bits Y0 to Y2 for specifying a first bit line pair (column) in a continuous access operation, and bank specifying signals B1 and B2, and a register control circuit 67 which generates wrap addresses WY0 to WY7, register ac |
