Giant Flaws...
Gary,
You wrote: thanks for your detailed note...however one giant flaw in your and SSTI's line of reasoning is that should demand for flash be met or dry up, the giants such as Intel and AMD will no longer be willing to forgo the lower end flash market. Indeed, dropping prices on their higher end products will inevitably kill off the lower end...I seriously doubt that SSTI can produce flash far cheaper than Intel, in terms of dollars per meg. In such bear markets, SSTI could wither away virtually "in a flash" (sic! could not resist!).
Okay, let's assume the worse case scenario: "should demand for flash be met or dry up, the giants such as Intel and AMD will no longer be willing to forgo the lower end flash market."
("lower end"…is this like a flash ghetto or what? Can't we leave it at just "low-density" :)
The good news for SSTI is we get to exclude the following companies from this discussion since SSTI benefits, through SuperFlash licensing, if any of these companies enter the low density market: Analog Devices, IBM, Motorola, National Semiconductor, Samsung Electronics Co. Ltd., SANYO Electric Co., Ltd., Seiko Epson Corp., TSMC-Acer Semiconductor Manufacturing Co. (TASMC) and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).
But that still leaves some giants of the likes of INTEL, AMD, Hitachi,, etc. How could SSTI compete?
You "seriously doubt that SSTI can produce flash far cheaper than Intel, in terms of dollars per meg." But wait! Intel just left the low-density market, licensing only SSTI to supply flash memory products compatible with Intel's 800 Series Hub Architecture chipsets! But just for fun, let me see if I can convince you otherwise. (Most of the following can be referenced from the flash technical paper: ssti.com )
There are three major approaches to producing low-density flash memory (EEPROMs):
The "thin oxide stacked gate" approach;
The "thin oxide two transistor cell"; and
The "thick oxide split-gate" patented by SSTI.
Each is a random access approaches, e.g., NOR type flash. A variation of the two transistor cell is also used by manufacturers for sequential access approaches, e.g., NAND (SNDK). Interestingly, the SSTI split-gate cell may also be used for sequential access architectures. According to SSTI's IR, this allows SSTI to move up the food chain into higher density / data storage flash. Any competitor's sequential access NAND flash is inappropriate for code storage, so in a sense it is a one-way street. SSTI is already beginning to move up, claiming the fastest read/write data transfer rates for their 96 Mbyte CompactFlash Card. For a further discussion on NOR versus NAND see:
nikkeibp.asiabiztech.com
Flash memories, and especially low-density flash memory is most readily compared on a performance, cost, reliability, and technology basis. Performance, cost, and reliability are directly related to the design and wafer process technology. SSTI's SuperFlash technology is superior because it typically uses a simpler process with fewer masking layers, compared with the other flash EEPROM approaches. Fewer masking steps significantly reduces the cost of manufacturing a wafer. Reliability is improved by reducing the latent defect density, i.e., fewer layers are exposed to possible defect causing mechanisms." These advantages translate into significant cost and reliability benefits for the user.
Manufacturing processes are the primary drivers for cost and reliability and it is here that INTEL, AMD and others must compete. Naturally, fewer operational steps in the manufacturing process will lower the cost of manufacturing and also increase the resulting product reliability.
So let's do a quick (real quick!) comparison of the three process:
"Stacked gate" flash requires extremely tight process controls. The relatively thin oxide layer requires a high level of oxide purity. The number of masking layers is at least 19.
With "two transistor thin oxide" processing, the formation of a very thin oxide is required. Therefore the oxide must be of very high integrity and low defect density, and thus it is difficult to manufacture. The number of masking layers is again at least 19.
"Thick oxide split gate", as its name implies overcomes the inherent weakness of thin oxides (purity, defect density…) and the number of masking layers is only 14.
MANUFACTURING PROCESS COMPARISONS
Stacked Gate Two Transistor SST
# Masking Layers 19-21 19-21 14
CMOS Logic Compatible Difficult Difficult Easy
Standard Oxide Process No No Yes
Fab Transferable Very Difficult Difficult Moderate
Reliablity
You know that the purpose of flash memory is to provide reprogrammable nonvolatile storage of information. The key here is "reprogrammable", because this is where failure rates and reliability come into play. Remember the words "thick oxide split-gate" process, patented by SSTI - here is why it significantly improves reliability over its competitors.
Without getting boringly technical, all floating gate structures use the same basic concept in doing their job. Charge (+, -) stored on the floating gate sets the transistor to a logical "1" or "0".
Reprogrammability requires the device be able to be altered. Reprogrammability requires the movement of electrons (wait - don't go to sleep…this is almost over!) The more times the device is altered, the more movement of electrons. It is this movement that destroys the insulation around the floating gate. Hence SSTI's thick oxide is mo' better'…
FAILURE MECHANISMS COMPARISONS
Failure Mechanisms Stacked Gate Two Transistor SST
Leaky Bit Medium High Low
Oxide Rupture Low High Low
Overerase High N/A N/A
Electromigration High Low Low
Contact Spiking High Low Low
Interface Trapping High Low Low
Most industry observers believe that in the near future, 164K is all that is going to be required for flash code storage. Therefore unless Intel or AMD invent a new disruptive manufacturing process, SSTI will own the low-density (not lower end!) flash market. IMO
Hope I've helped,
& Good luck,
Eric |
