Designers get physical with new tools
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FRIDAY, JULY 7, 2000 11:57:00 PM EST
Jul. 07, 2000 (Electronic Engineering Times - CMP via COMTEX) -- SAN JOSE, CALIF. - The new crop of physical-synthesis and physical-design tools that entered the EDA landscape with trumpets blaring is starting to reshape chip design, according to designers who have used them. Nevertheless, the tools still have a way to go before they deliver on their promise of revolutionizing design automation, the engineers say.
Exclusive interviews with designers who have taken tools like Avanti's Jupiter; Cadence's Envisia PKS; Magma's Blast Chip; Monterey's Dolphin; Sapphire's FormIT; Silicon Perspective's First Encounter; and Synopsys' Physical Compiler all the way through (or very close to) tapeout reveal that they can save substantial amounts of design time. All of these tools address the No. 1 concern of many chip designers: reaching timing closure without numerous iterations between synthesis and layout.
What's not yet clear is whether the tools actually produce faster or smaller chips. Many are lacking features that designers want, such as power optimization, engineering change order (ECO) handling, clock tree synthesis, scan chain insertion and test generation. Some still need to become more reliable and mature.
Still, the results can be impressive. Word of chip makers saving three man-months of effort (with Physical Compiler and Envisia PKS), and another reaching in an afternoon a floor plan similar to one that took four months to accomplish (First Encounter), has designers throughout the industry eager to take these babies out for a spin.
In physical design, few companies have made such bold claims as Magma Design Automation and Monterey Design Systems, both of which offer complete IC placement and routing systems that claim significant advantages over existing tools from Cadence and Avanti. But until very recently, both Magma and Monterey have been unable to name customers who have designed actual chips with their products.
Magma now has one in Govind Kizhepat, founder, chairman and vice president of engineering for iCompression (Santa Clara, Calif.), a digital video chip company now in the process of being acquired by GlobeSpan (Red Bank, N.J.). Kizhepat used Magma's latest offering, Blast Chip, on selected blocks in a 4 million-gate voice-over-Internet Protocol chip that's nearing tapeout. The largest of these blocks was nearly 1 million gates. Kizhepat reports that Blast Chip-which includes a complete register-transfer-level (RTL) synthesis capability as well as placement and routing-was able to meet the targeted 200-MHz timing with far fewer iterations than with iCompression's standard design flow, which includes Synopsys synthesis and Cadence layout products.
Guarded views
But that doesn't mean the Synopsys and Cadence tools are going out the window. "So far, it's promising, but we are not eliminating any [other] tools just yet," said Kizhepat. "Blast Chip has a ways to go in terms of being more reliable and stable."
Kizhepat said Blast Chip results in a slight area increase-around 10 percent-that he termed "tolerable" and well worth the much faster timing convergence. Still, he noted, the tool does not have all the capabilities of Synopsys' RTL synthesis, including DesignWare components, ECO handling and power optimization. It's thus not a complete replacement for Synopsys' Design Compiler-yet.
In addition to improved reliability, Kizhepat said he'd like to see Blast Chip offer better crosstalk and noise analysis, along with power optimization. And while the tool can handle a million-gate block in a little over a day, he'd also like to see the run-time improved. Ultimately, Kizhepat said he would like to see links to higher-level languages, such as Superlog or C/C++.
For its part, Monterey was unable to provide the name of a customer that has taped out a chip with its Dolphin placement and routing product. But Mike Fazeli, worldwide EDA manager for DSP-based designs at Texas Instruments Inc. (Dallas), said TI plans to move the product into a production flow.
"The test cases and examples we've run makes us believe we can see a significant reduction in cycle time to achieve timing closure," said Fazeli, who is currently evaluating Dolphin. "Because it's an integrated flow, we won't need translators to go from one design system to another."
It's too early to quantify the savings in terms of weeks or months, Fazeli added.
Though TI is focusing on cutting design time, as opposed to boosting performance, Fazeli said the side effect of reducing iterations should be more opportunity for trimming die size and improving chip performance.
Fazeli called TI a "driver customer" that is working with Monterey on the development of Dolphin. TI is pushing to make sure Dolphin has the ability to do "full chip integration," he said, and it also wants Dolphin to offer more of a "streamlined" flow with minimal user intervention.
Hermant Joshi, member of the technical staff at TI, said he'd like to see Monterey improve Dolphin's signal integrity and noise analysis capabilities. Joshi said that Monterey responds very quickly when TI runs into problems or bugs with the tool.
"We see that Dolphin is going to help us with a certain class of designs. I would classify those to be the sub-200-MHz designs where we're looking for cycle time improvements," said Fazeli. He emphasized that TI is not going to displace its existing physical-design tools, which are part of optimized flows already in place for specific applications.
Improving synthesis
Dolphin is currently a placement and routing tool that does not offer RTL synthesis. For that job, Fazeli uses Synopsys Inc.'s new Physical Compiler, which combines synthesis with what's billed as a complete placement capability. TI is further along with Physical Compiler than with Dolphin, having used it on an ARM925T core that's been completed and is nearing tapeout in a TI wireless-communications chip.
Fazeli said TI started using Physical Compiler in the fall of 1999, at first running the tool in parallel with Design Compiler to compare the results. "Around November we decided that there were so many good results with Physical Compiler that we [would] just concentrate on the Physical Compiler flow," he said.
It took a little while to get the tool in place, he said, but once it was set up, TI designers were able to get timing closure with only one minor iteration. Correlation between Physical Compiler's predicted timing and actual postroute timing was within 5 percent, said Fazeli, whereas in the past correlations were sometimes "totally off."
Rakesh Patnaik, program manager for wireless communications at TI, estimated that Physical Compiler saved three man-months of effort with the ARM core. An added bonus, he said, was that he could look at Physical Compiler and tell what was going on with the layout.
Although Physical Compiler and Dolphin both do placement, Fazeli said he believes there's a possibility of using the two together in a design flow. "There are overlapping areas, but I see them as more complementary." Fazeli said TI isn't sure which tool's placement would ultimately prevail.
Not having detailed routing in Physical Compiler is a drawback, he said, adding that he hopes Synopsys will add it. Patnaik noted that Physical Compiler lacks clock tree synthesis, power optimization and full support for test-all capabilities that he'd like to see.
Physical Compiler has a direct competitor in Cadence Design Systems Inc.'s Envisia PKS, which likewise combines synthesis with placement and global routing. Envisia PKS is based on Ambit synthesis technology. Recently Cadence added PKS capabilities to its Silicon Ensemble layout system, claiming a complete RTL-to-GDSII capability, although Cadence generally expects to sell synthesis and layout separately.
The first publicly acknowledged PKS tapeout was from EmpowerTel Networks (Milpitas, Calif.), an early user of the Ambit synthesis tools. Jayan Ramankutty, vice president of corporate engineering there, said his company used PKS on four MIPS processors, each around 90,000 gates of random logic plus cache, in a telecom switch with around 3 million gates. The cache, he said, was especially problematic in terms of setup and hold times.
"Initially we started without PKS, but achieving our timing-closure goals was becoming almost impossible," Ramankutty said. "We were over budget by two to three months." Wire-load models from synthesis, he said, could be off by as much as 25 to 30 percent from postroute timing results.
'A one-shot deal'
EmpowerTel was able to get PKS up and running very quickly, Ramankutty said, and the results were compelling. Instead of 30 percent off, the timing numbers that came out of PKS were within 3 percent of post-route results. "We didn't have any iterations-it was basically a one-shot deal," he added.
EmpowerTel used Silicon Ensemble to finalize the placement, as well as for clock tree synthesis and detailed routing. Ramankutty said third-party tools were needed for scan insertion.
In addition to saving three to four man-months, Ramankutty said, PKS resulted in a smaller chip. But PKS and other chip design tools share a common weakness, he said: lack of an ECO capability. If there's a change in the RTL design, "you've got to go back and start from scratch." What Ramankutty would really like to see is an ECO process that retains not only the design, but the placement as well.
The new physical-synthesis and physical-design tools from Magma, Monterey, Synopsys and Cadence all appear competitive with Avanti Corp.'s widely used Apollo layout system. But Avanti ups the ante with Jupiter, which provides RTL design planning, synthesis, optimization and full placement. Though not positioned as a replacement for Synopsys' Design Compiler, Jupiter promises greatly reduced iterations.
Kim Lau, CAD specialist at Motorola's Imaging Systems Division (Austin, Texas), hasn't taped out a chip with Jupiter, but he's putting the tool through its paces on an existing ColdFire chip design. Lau said he's using Jupiter as a "fast prototyping" tool with the goals of reducing design time, cutting die size and boosting chip performance.
How big, how fast?
Lau uses Jupiter to do RTL floor planning, placement and global routing. He runs its fast synthesis engine to get timing information. Then, he uses Synopsys' Design Compiler to synthesize individual blocks. Jupiter, Lau explained, does not offer a "full synthesis" capability. "When I do floor planning, I can get an idea of how fast the chip will run, how big it will be, and I can also fix some of the power," Lau said. "We don't need to wait until the routing, which would be several months later."
Lau said that Jupiter also offers a good postsynthesis optimization capability, including logic restructuring, and goes on to do a full placement and global routing. Lau said he's looked at the other new physical-synthesis and physical-design tools and found them lacking in comparison.
"Jupiter is a complete package," Lau said. "Some of the other tools only check placement-they don't do global routing. Some can't do clock trees, some can't do scan optimization, some can't do formal verification. I don't think a point-tool solution is going to fix all the problems."
But Jupiter is not perfect. Lau said the timing engine needs to be improved, and that optimization requires several passes. He'd like better support for Cadence's Verilog-XL simulator.
Given the wealth of synthesis tools and complete place-and-route schemes out there, some people question the viability of tools from Sapphire Design Automation and Silicon Perspective, which offer floor planning, placement and optimization. These have been called "glue" solutions because they fit between synthesis and routing, adding an extra tool to the flow.
And yet, both solutions are available now, and they appear to be stable and mature. Both companies can point to tapeouts and satisfied customers.
Microprocessor vendor Sandcraft (Mountain View, Calif.) has taped out a chip using Sapphire's FormIT, which provides electrical analysis, placement and optimization. Salah Gasti, director of CAD for Sandcraft, said FormIT helped his company achieve a better placement and increase the accuracy of preroute timing estimates.
Gasti used FormIT on the random-logic portion of a 64-bit MIPS processor. He declined to name his placement and routing supplier, but said FormIT offered better placement results 80 percent of the time. Its ability to upsize and downsize buffers, and to optimize selected paths, helped with timing closure, Gasti said.
'One-pass process'
"In an earlier generation there might be a one-third difference between what synthesis says, and what we have," said Gasti. "When we went through Sapphire, that difference went down to 10 percent. Now we have a one-pass process, which allows things to be done faster."
Still, "The placement may be fine, but if you don't have a global router, you're going to end up with problems such as congestion," he said.
Silicon Perspective's First Encounter combines partitioning, floor planning, placement, trial routing, parasitic extraction and timing optimization. Edward Yang, senior design engineer at AMD Inc. (Sunnyvale, Calif.), brought First Encounter into a troubled chip design project late in the game, and quickly reached timing closure on an Ethernet switch IC.
The chip had a lot of long nets, Yang explained, and his group was struggling through numerous iterations between Avanti layout and Synopsys synthesis tools. It was taking about a week to go through a single layout and extraction cycle. Far behind schedule, AMD turned to First Encounter, and within an afternoon Silicon Perspective application engineers generated a floor plan that was similar to the one AMD had created through four months of work.
Yang said First Encounter gave him quick, accurate timing estimates. As for the lack of detailed routing, "It's a trade-off. Right now what I appreciate is the speed."
DETAILED INTERVIEWS WITH MOST OF THESE DESIGNERS ARE AVAILABLE ONLINE AT WWW.EEDESIGN.COM.
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By: Richard Goering Copyright 2000 CMP Media Inc. |
