SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Rambus (RMBS) - Eagle or Penguin
RMBS 116.31-4.4%2:34 PM EST
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Dan3 who wrote (46837)7/12/2000 4:37:50 PM
From: Tenchusatsu  Read Replies (1) of 93625
 
Dan, <Do you realize that, internally, coppermine has a 128 bit wide connection between the core and the cache? Dual DDR would be a perfect match for Coppermine.>

First of all, Coppermine has a 256-bit wide connection between the core and L2 cache.

Second, AMD's Thunderbird only has a 64-bit wide connection between core and L2. Would you conclude that T-bird needs dual-DDR less than Coppermine? I wouldn't.

Finally, the width of the L2 connection really has nothing to do with the width of the DRAM channel. As long as the DRAM channel can provide the necessary amount of bandwidth without impacting latency too much, the width of the DRAM channel doesn't matter. I don't know why you're saying otherwise.

<Willamette will have an internal bus at least as wide as Coppermine. That's why the volume chipset for Willamette (Tulloch) isn't going to be stuck with Rambus.>

How do you know both of these "facts"? And once again, why should the width of Willamette's internal bus matter?

Tenchusatsu
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  

HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2026 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News