Hi Tenchusatsu; I see that Dan3 has already admirably replied to this post, but I thought I would add a few comments...
You wrote: "There isn't much of a difference in latency between sending all of the bits at once, and packetizing the data."
At 800MHz, the difference between 64-bits at once, and 4x 16-bits is 3 800MHz clocks or 3.75ns. I believe we can agree on these numbers, the question is whether 3.75ns is much of a difference... With a processor running at 1.6GHz, that is two clocks. How many instructions do the new machines execute per clock? It is obvious that 3.75ns added to every memory read is a substantial latency difference, surely enough to be visible in modern computers.
What's most important, the latency issue, in terms of missed instruction cycles, gets worse and worse as we go to higher speed processors, just the territory that Rambus tells us will be the promised land for RDRAM performance heaven. (And by the way, I thought that the promised land started at 500MHz, not 1.6GHz, or at least that is what Rambus was saying 5 years ago.
Funny thing about those religious leaders, their predictions always seem to be postponing themselves out into the future.
-- Carl |
