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Politics : Formerly About Advanced Micro Devices
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To: Scumbria who wrote (120394)7/17/2000 1:11:43 AM
From: Cirruslvr  Read Replies (4) of 1571281
 
Scumbria - RE: Thunderbird/Durons 64bit L2 cache data path

Straight from AMD:

"Unlike competing x86 processors—including Intel’s Pentium III processor—the AMD
Athlon processor features an L1 cache large enough to enable a high hit rate while
significantly reducing and minimizing bandwidth demands on the processor’s L2 cache.
For this reason, expanding the width of the L2 bus—currently 64 bits—offers little or no
benefit to overall performance. Emphasizing the high cache hit rates enabled by the new
AMD Athlon processor’s large L1 cache and exclusive L2 cache architecture, extensive
application performance testing shows that increasing the L2 bus width from 64 bits to 256
bits offers little or no significant impact to overall processor performance. Processors with
much smaller L1 caches need to be refilled more often and typically require a higher L2
bandwidth interface to help offset the shortcomings of their small L1 cache size."

amd.com

I'm very confident AMD's engineers know what they are doing.

BUT, here is what I see:

(Assuming same platforms)

Athlon Classic thoroughly outperforms first PIII (Katmai).

Cumine catches up to Athlon Classic.

Thunderbird is faster than Cumine, but NOT THOROUGHLY.

The ONLY changes to these processors that we know of is the L2 cache.

Potential answers:

1. Prior to the L2 cache going on die, the P6 was ALWAYS underfed, but is a VERY efficient design whose full performance wasn't attainable until the cache went on die.

2. Athlon's HUGE L1 cache SIGNIFICANTLY reduces the need for L2 cache access, and therefore doesn't benefit as much as PIII from faster L2 cache.

3. AMD's interpretation of "no significant impact" is significantly different from mine.

4. There is a bottleneck somewhere within the Athlon.

5. The P6 is just THAT good.

What do you think after reading AMD's explanation?

Thanks to Hans de Vries for the link.
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