Formerly About Advanced Micro Devices Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Scumbria who wrote (120404)	7/17/2000 3:01:27 AM
From: Hans de Vries	Read Replies (2) of 1571769

Sumbria: I only partially buy AMD's justification for the narrow L2 datapath. Eleven cycles of L2 latency is too long, and undoubtably has a significant impact on performance. The T-Bird L2 is certainly less important than the PIII L2, but a faster L2 would improve benchmark scores by several percent. The performance difference between a 64 bit and a 256 bit bus will increase significantly when the initial latency decreases from the current 11 cycles to something in the order of 6 like in the P3. So: The relatively long latency to the first critical word partly hides the disadvantages of the narrow 64 bit bus. The 64 bit bus increases also the potential latency for a second word accessed in the same cache line which can take up to 8 cycles more. (The time it takes to load the entire line). T-bird L2: ========== latency to first word in cache line: 11 cycles latency to second word in same cache line: 11..19 cycles PIII L2: ========== latency to first word in cache line: 6 cycles latency to second word in same cache line: 6 cycles Regards, Hans.

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next