Here's another article that adds more context to the CoWare/
Interdigital/Nokia joint venture on virtual components.
Contrary to popular belief, Nokia's handset business is not facing commoditization because the low-end is already a commodity market. If not for nible product development, astute brand building and its world-class process that allows it to use up to 80% common parts for its low-end, mid-range and high-end handsets, Nokia would already be in the same position as Motorola and Ericsson.
After having moved 79 million handsets last year, it is becoming clear that Nokia is best positioned to weather the challenge of the Japanese manufacturers, which typically refresh their product lines every 3 months.
That kind of competition is typical of the consumer electronics business and requires state of the art EDA tools.
Circuit density forces paradigm shift
By Ram Gopalan, VP Business Development, Cognigine Corp., Fremont, Calif.
EE Times
July 10, 2000 (11:45 a.m. EST)
Paradigm shifts in the storage industry offer a view of things to come in the silicon world. Only 15 years ago storage capacity cost $40 a megabyte; today it's 1 cent and going lower. Meanwhile, storage density is growing at a compound annual growth rate in excess of 60 percent, making storage capacity a commodity. To illustrate how software applications tend to be large and use storage capacity very indiscriminately, take a recent upgrade of Windows98: it required 110 Mbytes to store the old files.
A similar phenomenon is threatening to commoditize the silicon transistor/gate. Paradigm shifts in semiconductor technology tend to take hold gradually. The slow migration from schematic capture to Verilog-RTL-based design is one example. Moore's Law continues relentlessly, driving potential transistor counts upward at a 60 percent compound annual growth rate. Today's 0.18-micron semiconductor technology enables a density of 3 million gates on a square centimeter of silicon. At the same time, average system-on-chip (SoC) designs today are heavily I/O driven. That results in pad-limited die cavities on the order of 5 cm2, which would potentially imply a 15 million gate design. That's like building a 100-story skyscraper brick by brick: it may be doable but it's not practical.
Hard realities are setting in for the extreme submicron design world. Even sub-submicron (0.08) levels will be along in the very near future. Migration to finer geometry processes results in more masks and more intricate ones, making mask set costs and fabrication NREs prohibitive. Multimillion-gate designs at the finer geometries are making the SoC designs more interconnect-centric. That, in turn, raises the need for accurate modeling of the interconnect, power density, metal migration, capacitive and inductive coupling, thermal issues and so on. Verifying and testing these SoC designs requires large teams, hampering design productivity.
Paradigm shifts in system design have occurred frequently over the last 50 years. Common practice has progressed from breadboarding, to handpacking, to schematic capture, to behavioral RTL, to cell-based synthesis. Today's cell-based synthesis is clearly running out of steam when confronted with the challenge of extreme submicron and sub-submicron SoC integration. The next design paradigm in semiconductor technology is now due.
It should reach several goals. It must significantly simplify and increase the confidence of design and verification of embedded SoCs in a short time-to-market. It must embrace a hardware/software codesign concept. That means instead of designing new hardware for every SoC application, there would be a standard off-the-shelf hardware platform chip from which a family of applications could be created. Changes would be implemented in the firmware and not the hardware. This should also result in economies of scale because such chips could be made in greater volumes.
This new paradigm of platform-based embedded SoC is starting to take root for economic and practical reasons rather than conceptual and architectural ones. Embedded SoC platforms are created by compiling a set of programmable processors. As with high transistor counts becoming a commodity, large size SoC platforms make inefficiencies at the gate level insignificant in the grand scheme of things. This amounts to replacing gate-level functionality with a scalable multiprocessing environment. Such environments comprise deeply embedded computing engines with configurable data paths, embedded memory stacks and innovative packet-like transmission mechanisms. The transmission schemes enable them to talk to each other and the outside world without presenting a bottleneck for handling wire speed processes.
At first, these new hardware platforms will stiff competition from programmable hardware with hard-coded blocks optimized for vertical markets. Yet the phenomenal silicon densities achievable with the sub-submicron technology will make tortuous the path from acceptable behavioral RTL to a reliable physical design. This will force the paradigm shift to materialize into reality with a family of reconfigurable embedded SoC hardware platforms with their configuration and I/O optimized to address a broad application focus area. As embedded microcomputer cores get faster and smaller, they can do more and more. Tasks can be completed in software running on these hardware platforms instead of dedicated hardware. The hardware-only ASIC as we know it today will, in the not-too-distant future, become a sandwich of a hardware silicon platform and software that gives it the desired application flavor.
Processor trends
A recent trend observed in the announcements of reconfigurable communication processors and media processors exemplify this impending paradigm shift. Companies like Chameleon Systems, Cognigine, Improv Systems and Malleable Technologies are among the coming breed of players taking cues from the FPGA, DSP, RISC and VLIW communities to sow the seeds of this shift. Such companies are turning out hardware platforms tuned for the communication processing areas with varying levels of on-the-fly hardware reconfigurability and software programmability.
A number of approaches have been taken to address this paradigm shift at the 0.25-micron silicon technology level. Such efforts, while admirable, have barely scratched the surface of this paradigm shift. There is a lot to come with the advent of the sub-submicron silicon technology. The simplest approach is that used by companies like Triscend. It uses a traditional FPGA matrix intricately connected with a simple CPU core amid an easy-to-use behavioral-level development environment.
Chameleon has taken that approach to the next level, using a 32-bit ARC processor as the executive controller in the platform. The processor oversees an internal 128-bit split-transaction bus used to communicate among the executive controller, peripherals and a reconfigurable processing fabric. The fabric consists of 32-bit data path units in lieu of a conventional FPGA matrix.
For its part, Improv Systems has created a high-performance hardware platform consisting of an array of configurable Jazz processing engines. It melds innovative multiprocessing techniques with VLIW processing techniques. The configurable data path architectures support wide data paths and essentially allow the computing engines to be tuned for RISC-like control operations or DSP-like signal-processing operations. This level of configurability is also achieved with a distributed internal shared memory structure that allows compute resources to produce or consume data without bandwidth limitations. That enables simultaneous access to memory from all computational resources and a higher number of operations per cycle.
Flexible deployment
Central to the successful deployment of these configurable embedded SoC platforms is the availability of compilers, real-time OS, a user-friendly development environment and a library of software IP modules. Software IP modules let designers realize their functionality in software in a matter of months rather than years. They also give designers complete freedom to implement product variations and functionality changes at any time.
By 2010, if you want to avoid designing the wrong billion-transistor chip with an army for a design team, reconfigurable hardware platforms will become a necessity, not just an alternative for implementing embedded SoC. We won't need hardware designers anymore. In time, only three giant true semiconductor companies will be left with about a dozen hardware platform designs. Instead of doing hardware design, everybody will be writing firmware and software in the name of chip design.
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