ML:+ve on EDA sector,SNPS'PC has more engagements over PKS
Excerpts fr ML Research on CDN, 7/19/00
Cadence noted that its next-generation products and
technology, particularly Envisia Ambit with PKS
technology for physical synthesis and the recently
announced Silicon Ensemble with PKS (SE-PKS), are
being well received at customer evaluations and are on
target for availability throughout FY00. SE-PKS should
turn out to be an important upgrade opportunity for
Cadence in its installed base, just as Physical Compiler
could turn out to be a strong upgrade opportunity from
Design Compiler for Synopsys (SNPS, $43, C-3-1-9).
The company announced 10 new SP&R orders, compared
with 5 orders in 1Q00 (bringing the total to date to 26
orders), and that it is engaged at 60 accounts, for which it
is in the process of adding technical support (still fewer
than the number of accounts Synopsys has cited as
evaluating its "physical syntheses" solutions); as with its
peers addressing this new chip design methodology
opportunity, technical support capacity has been a key
issue and Cadence is making a prudent decision to invest
more here. The competition in this new integrated design
methodology will be a critical feature of the EDA market
this year, with effects that will go beyond just 2000 [for
related comments, see our Technical software industry
update, dated January 6, 2000] to increase its market share
in "conventional synthesis" (i.e., Ambit) and in
"optimization place and route" (i.e., Silicon Ensemble with
PKS, or SE-PKS) over the next three years. The company
claims its competitive edge will in having a common
solution for both front-end (i.e., for improving
predictability to timing-closure) and back-end designers.
By 2001, we ought to begin to see a
more normal growth rate for the company, and one that
presumably would be at least in line with industry growth.
In that regard, the company remained notably enthused
about the outlook for the industry through this year and
next given the combined effects of new end market
growth, new products, services, and customer retooling.
We concur with that view of being still in the early stages
of the EDA retooling and growth cycle.
The Electronics Design Process
Our thesis on the EDA sector has been that we are still in
the early stages of what could be a several year process of
renewed investment in new design technology and
methodologies. We expect that Cadence, not simply
because of its size, ought to be a key beneficiary of that
process, allowing it to grow perhaps at above the generally
assumed industry growth rate next year. The growth
opportunities stem from the use of more electronics in
more products, and more markets, e.g., wireless and wired
products, information appliances, and "pervasive
computing". Indeed, the company expects there could be
two “retooling” phases, one, starting now, for deep
submicron implementation (0.18 um and below, which is
already on a steep ramp in terms of design starts) from
2000-2002, and another, for “the real era of system on
chip”. A recovery and retooling of design processes in
Japan and the rest of Asia would be a key part of this
process or cycle as well.
So, over the course of what could turn out to be these two
parallel retooling phases, Cadence expects to be in the
position of helping its customers to re-engineer their
practices and to help them "stitch together" virtual product
development environments, which would include the
integration of electronics supply chains (which is where in
part the iCadence initiative comes into play). The net
effect should be a larger addressable market than for
design tools alone, though those would still be in our
opinion a necessary condition for long-term
competitiveness and revenue growth.
The key areas or process steps which the company's
products address include system level design (which
includes system evaluation & analysis and algorithm
implementation and which is expected to be the fastest
growing segment), functional verification (including
simulation and emulation), digital IC design (synthesis,
place and route), custom IC design, physical verification
(where Cadence fell to second place behind Mentor
Graphics), PCB, physical design, and of course the closely
watched "physical synthesis" or "synthesis place and
route" (S, P&R) area. |
