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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 215.00+0.7%3:59 PM EST
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To: Hans de Vries who wrote (2598)7/28/2000 1:28:28 AM
From: Pravin KamdarRead Replies (1) of 275872
 
Hans,

The S/D contact regions 98 are formed on the vertical side-walls 78
so that only a minimal amount of the horizontal surface 12 of the substrate 10 is
used to form electrical contacts. The lateral source/drain transistor 1 realizes a
significant reduction in lateral dimension 17 in comparison to lateral dimension 50 of
the transistor shown in FIG. 3. The S/D contact regions 98 have a large surface
area that results in a reduced contact resistance than is attainable using
conventional techniques and structures. A lowering in S/D contact resistance
enhances transistor performance.

Is dimension 50 the distance between the inner source/drain contact edges on a conventional transistor? If not, is seems like the the source/drain contact regions 6 are not being accounted for in the required lateral dimension (wish I had all the drawings). This sounds like a good idea. With additional benefits of noise isolation and latch-up prevention (the isolation preventing the creation of parasitic lateral bipolars). How many processing steps and mask layers does it add?

The thought of AMD using a new transistor design with new processing steps scares the hell out of me. Any manufacturing glitches will kill this stock.

Thanks for the info.

Pravin.
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