Sorry to interrupt all the fun again but I do have some technical questions which seem best suited for the EE's on this thread.
The following article appeared yesterday:
ebnonline.com
Also, Samsung Electronics Co. Ltd. is developing a four-memory-bank configuration-significantly less than the current 32-bank Direct RDRAM design, said Yong Joo Han, manager of DRAM product planning for the Memory Product and Technology Division at Samsung. “This will cut the size of the chip to only 5% larger than comparably [sized] SDRAM, lowering production costs greatly,” Kanadjian said.
Samsung, the major Direct RDRAM supplier, also is planning to use a low-cost consumer-chip package for PC applications similar to what Toshiba is using in units shipped for the Sony PlayStation II. The current Direct RDRAM µBGA package, which must be licensed from Tessera Inc., is more costly than the new one in development, according to other DRAM makers.
My questions are these:
1) Why did RMBS design DRDRAM with 32 banks in the first place?
2) Will Samsung's design improvements still consist of a packetized architecture?
3) Although these improvements will clearly improve the cost structure what will they do to (i) performance, assuming the structure is still optimized for packet transfer?; and (ii) power usage, under the same assumptions?
With all due respect to the posters here, it seems to me that the future prospects of RMBS are tied much more securely to the affects of Samsung's work than their legal efforts to obtain SDRAM payments.
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